參數(shù)資料
型號(hào)： HSP43881883
廠商： Intersil Corporation
英文描述： Digital Filter
中文描述： 數(shù)字濾波
文件頁(yè)數(shù)： 13/21頁(yè)
文件大?。?/td> 148K
代理商： HSP43881883
13
Cascade Configuration
To design a filter length L>8, L/8 DFs are cascaded by
connecting the COUT0-7 outputs of the (i)th DF to the CIN0-
7 inputs of the (i+1)th DF. The DIN0-7 inputs and SUM0-25
outputs of all the DFs are also tied together. A specific
example of two cascaded DFs illustrates the technique
(Figure 5). Timing (Figure 6) is similar to the simple 8-tap
FIR, except the ERASE and SENBL/SENBH signals must be
enabled independently for the two DFs in order to clear the
correct accumulators and enable the SUM0-25 output
signals at the proper times.
Single DF Configuration
Using a single DF, a filter of length L>8 can be constructed
by processing in L/8 passes as illustrated in the following
table (Table 2) for a 16-tap FIR. Each pass is composed of
Tp = 7 + L cycles and computes eight output samples. In
pass i, the sample with indices i*8 to i*8 +(L1) enter the
DIN0-7 inputs. The coefficients C
0
-C
L -1
enter the CIN0-7
inputs, followed by seven zeros. As these zeros are entered,
the result samples are output and the accumulators reset.
Initial filing of the pipeline is not shown in this sequence
table. Filter outputs can be put through a FIFO to even out
the sample rate.
Extended Coefficient and Data Sample
Word Size
The sample and coefficient word size can be extended by
utilizing several DFs in parallel to get the maximum sample
rate or a single DF with resulting lower sample rates. The
technique is to compute partial products of 8 x 8 and
combine these partial products by shifting and adding to
obtain the final result. The shifting and adding can be
accomplished with external adders (at full speed) or with the
DF's shift and add mechanism contained in its output stage
(at reduced speed).
Decimation/Resampling
The HSP43881 DF provides a mechanism for decimating by
factors of 2, 3, or 4. From the DF filter cell block diagram
(Figure 1), note the three D registers and two multiplexers in
the coefficient path through the cell. These allow the
coefficients to be delayed by 1, 2, or 3 clocks through the
cell. The sequence table (Table 3) for a decimate by two filter
illustrates the technique (internal cell pipelining ignored for
simplicity).
Detailed timing for a 30MHz input sample rate, 15MHz
output sample rate (i.e., decimate by two), 16-tap FIR filter,
including pipelining, is shown in Figure 7. This filter requires
only a single HSP43881 DF.
HSP43881
相關(guān)PDF資料
PDF描述
HSP43891GC-20 Digital Filter
HSP43891GC-25 Digital Filter
HSP43891GC-30 Digital Filter
HSP43891JC-20 Digital Filter
HSP43891JC-25 Digital Filter
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HSP43881GC-20 制造商:Harris Corporation 功能描述:
HSP43881GC-25 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述:
HSP43881GC-30 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Digital Filter
HSP43881GM-25/883 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Digital Filter
HSP43881JC-20 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述:
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