參數(shù)資料
型號(hào)： HSP43220JC-25Z
廠商： Intersil
文件頁(yè)數(shù)： 16/21頁(yè)
文件大?。?/td> 0K
描述： IC DECIMATING DGTL FILTER 84PLCC
標(biāo)準(zhǔn)包裝： 15
濾波器類型： 數(shù)字
濾波器數(shù)： 4
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 84-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 84-PLCC（29.21x29.21）
包裝： 管件
4
FN2486.10
October 10, 2008
Integrator Section
The data from the shifter goes to the Integrator section.
This is a cascade of 5 integrator (or accumulator) stages,
which implement a low pass filter. Each accumulator is
implemented as an adder followed by a register in the feed
forward path. The integrator is clocked by the sample clock,
CK_IN as shown in Figure 2. The bit width of each integrator
stage goes from 66 bits at the first integrator down to 26 bits
at the output of the fifth integrator. Bit truncation is performed
at each integrator stage because the data in the integrator
stages is being accumulated and thus is growing, therefore
the lower bits become insignificant, and can be truncated
without losing significant data.
There are three signals that control the integrator section;
they are H_STAGES, H_BYP and RESET. In Figure 2 these
control signals have been decoded and are labelled
INT_EN1 - INT_EN5. The order of the filter is loaded via the
control bus and is called H_STAGES. H_STAGES is
decoded to provide the enables for each integrator stage.
When a given integrator stage is selected, the feedback path
is enabled and the integrator accumulates the current data
sample with the previous sum. The integrator section can be
put in bypass mode by the H_BYP bit. When H_BYP or
RESET is asserted, the feedback paths in all integrator
stages are cleared.
Decimation Register
The output of the Integrator section is latched into the
Decimation Register by CK_DEC. The output of the
Decimation register is cleared when RESET is asserted. The
HDF decimation rate = H_DRATE +1, which is defined as
HDEC for convenience.
FIGURE 1. HIGH ORDER DECIMATION FILTER FIGURE
FIGURE 2. INTEGRATOR
HDF FILTER SECTION
DEC
REG
INTEGRATOR
INPUT
REG
COMB FILTER
ROUND
REG
26
16
TO FIR
16
19
26
66
16
ISTART
COMB_EN1-5
H_GROWTH
INT_EN1-5
RESET
5
CK_IN
CK_DEC
TO FIR
STARTIN
STARTOUT
START
LOGIC
RESET
ASTARTIN
CK_IN
DATA
IN
ISTART
RESET
H_DRATE
H_BYP
CK_IN
CLOCK
DIVIDER
CONTROL
REGISTER LOGIC
A0-1
WR
CS
C_BUS
COMB_EN1-5
65
5
H_GROWTH
INT_EN1-5
CK DEC
5
6
DATA
SHIFTER
MUX
INT_EN5
REG
66
63
0
MUX
INT_EN4
REG
53
0
MUX
INT_EN3
REG
43
0
MUX
INT_EN2
REG
35
0
MUX
INT_EN1
REG
26
0
FROM
SHIFTER
TO
DECIMATION
REGISTER
CK
IN
∑
HSP43220
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