參數(shù)資料
型號: HSP43216JC-52Z
廠商: Intersil
文件頁數(shù): 15/20頁
文件大小: 0K
描述: IC HALFBAND FILTER 84-PLCC
標準包裝: 15
濾波器類型: 半帶
濾波器數(shù): 4
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 84-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 84-PLCC(29.21x29.21)
包裝: 管件
4
FN3365.10
October 6, 2008
Functional Description
The operation of the HSP43216 centers around a fixed
coefficient, 67-Tap, Halfband Filter Processor as shown in
Figure 1. The Halfband Filter Processor operates stand
alone to provide two fundamental modes of operation:
interpolate or decimate by two filtering of a real signal. In two
other modes, the Quadrature Up/Down Convert circuitry
operates together with the Filter Processor block to provide
fS/4 Down Conversion with decimate by 2 filtering or
Quadrature to Real Conversion.
In Down Convert and Decimate mode, a real input sample
stream is spectrally shifted by fS/4. Each component of the
resulting complex signal is then halfband filtered and
decimated by 2 to produce real and imaginary output
samples at half of the input data rate.
In Quadrature to Real Conversion mode, the real and
imaginary components of a quadrature input are interpolated
by two and halfband filtered. The filtered result is then
spectrally shifted by fS/4 and the real component of this
operation is output at twice the input sample rate.The
HSP43216 is configured for different operational modes by
setting the state of the mode control pins, MODE1-0 as
shown in Table 1.
Input Data Flow Controller
The Input Data Flow Controller routes data samples from the
AIN0-15 and BIN0-15 inputs to the internal processing
elements of the Halfband. The data routing paths are based
on mode of operation and are more fully discussed in the
Operational Modes section.
fS/4 Quadrature Down Convert Processor
The fS/4 Quadrature Down Convert Processor operates as a
Quadrature LO which provides the negative fS/4 spectral
shift required to center the upper sideband of a real input
signal at DC. This operation is equivalent to multiplying the
real sample stream, x(n), by the quadrature components of
the complex exponential e-j(π/2)n as given below:
R
E
G
M
U
X
fS/4
L.O.
MUX
1,-1,1,..
-1,1,-1,.
1
EVEN TAP
FILTER
MUX
1
...,2,-2,2
..,-2,2,-2
M
U
X
ODD TAP
FILTER
AIN0-15
BIN0-15
BOUT0-15
AOUT0-15
OEA
OEB
USB/LSB
R
E
G
R
E
G
R
E
G
R
E
G
R
E
G
R
E
G
R
E
G
R
E
G
R
N
D
F
M
T
R
E
G
R
E
G
R
N
D
F
M
T
R
E
G
R
E
G
R
E
G
R
E
G
2
Indicates elements which operate at CLK/2 when the INT/EXT control input is high.
SYNC
INT/EXT
RND0-2
FMT
MODE0-1
INPUT DATA FLOW
CONTROLLER
fS/4 QUADRATURE
DOWN CONVERT
67-TAP HALFBAND
FILTER
fS/4 QUADRATURE
UP CONVERT
OUTPUT DATA FLOW
CONTROLLER
PROCESSOR
DELAY 19
DELAY 2 - 35
SYNC
PROCESSOR
+
FIGURE 1. HALFBAND BLOCK DIAGRAM
CLK
USB/LSB
PIPELINE
TABLE 1. MODE SELECT TABLE
MODE1-0
MODE
00
Decimate by Two
01
Interpolate by Two
10
Down Convert and Decimate
11
Quadrature to Real Conversion
xn
()
e j πn2
()
xn
()
πn2
()
jx n
()
π
n2
()
sin
+
cos
=
(EQ. 1)
HSP43216
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