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參數資料
| 型號： | HSP43124SI-40 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 數字信號處理外設 |
| 英文描述： | Serial I/O Filter |
| 中文描述： | 1-BIT, DSP-DIGITAL FILTER, PDSO28 |
| 文件頁數： | 16/17頁 |
| 文件大?。?/td> | 144K |
| 代理商： | HSP43124SI-40 |
16
AC Test Load Circuit
AC Electrical Specifications
(Note 5) V
CC
= +4.75V to +5.25V, T
A
= 0
o
C to 70
o
C (Commercial)
V
CC
= +4.75V to +5.25V, T
A
= -40
o
C to 85
o
C (Industrial)
PARAMETER
SYMBOL
NOTES
45MHz
40MHz
33MHz
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
FCLK, SCLK Period
t
CP
22
-
25
-
30
-
ns
FCLK, SCLK High
t
CH
8
-
10
-
12
-
ns
FCLK, SCLK Low
t
CL
8
-
10
-
12
-
ns
Setup Time DIN, MXIN, SYNCIN, SYNCMX to
SCLK
t
DS
8
-
8
-
9
-
ns
Hold Time DIN, MXIN, SYNCIN, SYNCMX from
SCLK
t
DH
0
-
0
-
0
-
ns
Setup Time FSYNC to FCLK
t
SS
8
-
8
-
8
-
ns
Hold Time FSYNC from FCLK
t
SH
0
-
0
-
0
-
ns
Setup Time C0-7, A0-2 to Falling Edge of WR
t
WS
10
-
10
-
10
-
ns
Hold Time C0-7, A0-2 from Falling Edge of WR
t
WH
3
-
3
-
3
-
ns
Setup Time A0-2 to Falling Edge of RD
t
RS
10
-
10
-
10
-
ns
Hold Time A0-2 from Rising Edge of RD
t
RH
0
-
0
-
0
-
ns
WR High
t
WRH
10
-
10
-
12
-
ns
WR Low
t
WRL
10
-
10
-
12
-
ns
RD High
t
RDH
10
-
10
-
10
-
ns
RD Low to Data Valid
t
RDO
-
25
-
25
-
25
ns
RD High to Output Disable
t
OD
-
6
-
6
-
6
ns
FCLK to CLKOUT
t
FOC
-
12
-
13
-
14
ns
CLKOUT to SYNCOUT, DOUT
t
DO
-
8
-
9
-
10
ns
Output Rise, Fall Time
t
RF
Note 6
-
3
-
3
-
3
ns
NOTES:
5. AC tests performed with C
L
= 40pF, I
OL
= 5mA, and I
OH
= -5mA. Input reference level for FCLK and SCLK is 2.0V, all other inputs 1.5V. Test
V
IH
= 3.0V, V
IHC
= 4.0V, V
IL
= 0V.
6. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes.
EQUIVALENT CIRCUIT
C
L
(NOTE)
I
OH
1.5V
I
OL
DUT
SWITCH S1 OPEN FOR I
CCSB
AND I
CCOP
S
1
±
NOTE: Test head capacitance.
HSP43124
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