參數(shù)資料
型號: HS9-82C08RH
廠商: HARRIS SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: Radiation Hardened 8-Bit Bus Transceiver
中文描述: OCTAL LINE TRANSCEIVER, CDFP20
文件頁數(shù): 2/6頁
文件大小: 44K
代理商: HS9-82C08RH
2
HS-82C08RH
Spec Number
518057
Logic Diagram
NOTE: An Important caveat that is applicable to CMOS devices in general is that unused inputs should never be left floating. This rule applies
to inputs connected to a three-state bus. The need for external pull-up resistors during three-state bus conditions is eliminated by the
presence of regenerative latches on the following HS-82C08RH pins. A0-7 and B0-7 The functional block diagram depicts one of
these pins with the regenerative latch. When the CMOS driver assumes the high impedance state, the latch holds the bus in whatever
logic state (high or low) it was before the three-state condition. A transient drive current of
±
1.5mA at VDD/2
±
0.5V for 10ns is required
to switch the latch. Thus, CMOS device inputs connected to the bus are not allowed to float during three-state conditions.
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
METAL-SEAL PACKAGE (SBDIP) MIL-STD-1835, CDIP2-T20
TOP VIEW
20 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK) MIL-STD-1835, CDFP4-F20
TOP VIEW
PIN
DESCRIPTION
PIN
DESCRIPTION
A0-A7
Local Bus Data I/O Pins
T/R
Transmit/Receive Input
B0-B7
System Bus Data I/O Pins
OE
Active Low Output Enable
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
A0
A1
A2
A3
A4
A5
A7
A6
OE
GND
VDD
B1
B2
B3
B0
B4
B5
B6
B7
T/R
2
3
4
5
6
7
8
9
10
1
20
19
18
17
16
15
14
13
12
11
A0
A1
A2
A3
A4
A5
A6
A7
OE
GND
VDD
B0
B1
B2
B3
B4
B5
B6
B7
T/R
1
A0
TSB
TSB
B ENABLE
19
B0
2
A1
TSB
TSB
18
B1
3
A2
TSB
TSB
17
B2
4
A3
TSB
TSB
16
B3
5
A4
TSB
TSB
15
B4
6
A5
TSB
TSB
14
B5
7
A6
TSB
TSB
13
B6
8
A7
TSB
TSB
12
B7
A ENABLE
OE9
T/R11
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