參數(shù)資料
型號(hào)： HS8-RTX2010RH
廠商： Intersil Corporation
英文描述： Radiation Hardened Real Time Express⑩ Microcontroller
中文描述： 輻射加固實(shí)時(shí)快遞⑩微控制器
文件頁(yè)數(shù)： 14/36頁(yè)
文件大?。?/td> 406K
代理商： HS8-RTX2010RH
14
Memory Page Controller Registers
: The Code Page Register contains the value for the
current 32K-word Code page. See Figure 18 for bit field
assignments.
: The Index Page Register extends the Index Register
) by 5 bits; i.e., when a Subroutine Return is performed,
contains the Code page from which the subroutine
was called, and comprises the 5 most significant bits of the
top element of the Return Stack. See Figure 19. During
nonsubroutine operation, writing to
Code page value to be written to
directly to
does not push the Return Stack.
IPR
(
the
causes the current
. Reading or writing
: The Data Page Register contains the value for the
current 32K-word Data page. See Figure 20 for bit field
assignments.
: The User Page Register contains the value for the
current User page. See Figure 21 for bit field assignments.
: The User Base Address Register contains the base
address for User Memory Instructions. See Figure 21 for bit
field assignments.
0
1
2
3
4
5
6
7
8
9
PSF: PARAMETER STACK
START FLAG
PARAMETER SUBSTACK BITS:
= 00: EIGHT 32 WORD STACKS
= 01: FOUR 64 WORD STACKS
= 10: TWO 128 WORD STACKS
= 11: ONE 256 WORD STACK
PSU: PARAMETER
STACK UNDERFLOW LIMIT
0 - 31 WORDS FROM
BOTTOM OF SUBSTACK
RSF: RETURN STACK
START FLAG
RETURN SUBSTACK BITS:
= 00: EIGHT 32 WORD STACKS
= 01: FOUR 64 WORD STACKS
= 10: TWO 128 WORD STACKS
= 11: ONE 256 WORD STACK
RSU: RETURN STACK
UNDERFLOW LIMIT
0 - 31 WORDS FROM
BOTTOM OF SUBSTACK
SUR
15 1413121110
FIGURE 17.
BIT ASSIGNMENTS
SUR
CPR
0
1
2
3
4
5
6
7
11
8
9
10
12
13
14
15
CPR
MA16
MA17
MA18
MA19
RESERVED
(NOTE)
NOTE: Always read as ‘‘0’’. Should be set = 0 during Write operations.
FIGURE 18.
BIT ASSIGNMENTS
CPR
IPR
I
IPR
I
IPR
DPR
UPR
UBR
BIT ASSIGNMENTS DURING NON-SUBROUTINE OPERATIONS
I
IPR
9
0
1
2
3
4
5
6
7
8
BIT ASSIGNMENTS DURING SUBROUTINE OPERATIONS
DEFINES RETURN ADDRESS
TYPE OF RETURN
= 1: INTERRUPT RETURNS:
= 0: SUBROUTINE RETURNS:
OR SUBROUTINE CALL
STORED DURING INTERRUPT
I
IPR
8
1
9
0
1
2
3
4
5
6
7
8
USED FOR TEMPORARY
STORAGE OF VARIABLES,
LOOP COUNTS, AND
STREAM COUNTS
CURRENT CODE
PAGE VALUE
0
2
9
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
0
2
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
FIGURE 19.
AND
BIT ASSIGNMENTS
I
IPR
0
1
2
3
4
5
6
7
11
8
9
10
12
13
14
15
DPR
MA16
MA17
MA18
MA19
RESERVED
(NOTE)
NOTE: Always read as ‘‘0’’. Should be set = 0 during Write operations.
FIGURE 20.
BIT ASSIGNMENTS
DPR
0
1
2
3
4
5
6
7
11
8
9
10
12
13
14
15
USER PAGE
REGISTER
UBR
MA15 - MA06
0
1
2
3
4
5
6
7
11
8
9
10
12
13
14
15
I R
0
1
2
3
4
5
6
7
11
8
9
10
12
13
14
15
UPR
MA19
MA18
MA17
MA16
NOT USED TO GENERATE
THIS ADDRESS
INSTRUCTION
REGISTER
R
USER BASE
ADDRESS
REGISTER
RESERVED
(NOTE)
MA05
MA04
MA03
MA02
MA01
(
NOTE: Always read as ‘‘0’’. Should be set = 0 during Write operations.
FIGURE 21.
AND
UPR
UBR
BIT ASSIGNMENTS
HS-RTX2010RH
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