參數(shù)資料
型號(hào)： HS8-RTX2010RH
廠商： Intersil Corporation
英文描述： Radiation Hardened Real Time Express⑩ Microcontroller
中文描述： 輻射加固實(shí)時(shí)快遞⑩微控制器
文件頁(yè)數(shù)： 12/36頁(yè)
文件大?。?/td> 406K
代理商： HS8-RTX2010RH
12
: The Program Counter Register contains the address
of the next instruction to be fetched from Main Memory. At
RESET, the contents of
PC
are set to 0.
: The Index Register contains 16 bits of the 21-bit top
element of the Return Stack, and is also used to hold the
count for streamed and loop instructions (see Figure 19). In
addition,
can be used to hold data and can be written
from
. The contents of
either the push/pop mode in which values are moved to/from
stack memory as required, or in the read/write mode in
which the stack memory is not affected. The ASIC address
used for
determines what type of operation will be
performed (see Table 5). When the Streamed Instruction
Mode (see RTX Programmer’s Reference Manual) is used, a
count is written to
and the next instruction is executed
that number of times plus one (i.e., count + 1).
may be accessed in
: The Multi-Step Divide Register holds the divisor
during Step Divide operations, while the 32-bit dividend is in
and
.
may also be used as a general
purpose scratch pad register.
: The Square Root Register holds the intermediate
values used during Step Square Root calculations.
may also be used as a general purpose scratch pad register.
On-Chip Peripheral Registers
The HS-RTX2010RH has an on-chip Interrupt Controller, a
Memory Page Controller, two Stack Controllers, three
Timer/Counters, a Multiplier-Accumulator, a Barrel Shifter,
and a Leading Zero Detector. Each of these peripherals
utilizes on-chip registers to perform its functions.
Timer/Counter Registers
,
,
16-bit read-only registers which contain the current count
value for each of the three Timer/Counters. The counter is
decremented at each rising clock edge of TCLK. Reading
from these registers at any time does not disturb their
contents. The sequence of Timer/Counter operations is
shown in Figure 23 in the Timer/Counters section.
: The Timer/Counter Registers are
,
,
: The Timer Preload Registers are
write-only registers which contain the initial 16-bit count
values which are written to each timer. After a timer counts
down to zero, the preload register for that timer reloads its
initial count value to that timer register at the next rising clock
edge, synchronously with TCLK. Writing to these registers
causes the count to be loaded into the corresponding Timer/
Counter register on the following cycle.
Multiplier-Accumulator (MAC) Registers:
: The Multiplier High Product Register holds the most
significant 16 bits of the 32-bit product generated by the RTX
Multiplier. If the
register’s ROUND bit is set, this
register contains the rounded 16-bit output of the multiplier.
In the Accumulator context, this register holds the middle 16
bits of the MAC.
: The Multiplier Lower Product Register holds the least
significant 16 bits of the 32-bit product generated by the RTX
Multiplier. It is also the register which holds the least
significant 16 bits of the MAC Accumulator.
: The MAC Extension Register holds the most significant
16 bits of the MAC Accumulator. When using the Barrel Shifter,
this register holds the shift count. When using the Leading Zero
Detector, the leading zero count is stored in this register.
Interrupt Controller Registers
: The Interrupt Vector Register is a read-only register
which holds the current Interrupt Vector value. See Figure 12
and Table 4.
: The Interrupt Base/Control Register is used to store
the Interrupt Vector base address and to specify
configuration information for the processor, as indicated by
the bit assignments in Figure 13.
R/W; CARRY
R/W; COMPLEX CARRY
R/W; BYTE ORDER BIT
RESETS TO 0. MODES:
SET INTERRUPT DISABLE;
0 = INT. ENABLED;
1 = INT. DISABLED
RESERVED (NOTE)
NMI MODE
1 = RETURN FROM NMI POSSIBLE
0 = NO RETURN FROM NMI
(RTX 2000 MODE)
WRITE - ONLY (READS AS 0);
0 = ADDRESSING MODE 0
R/W; BOOT
DRIVES OUTPUT SIGNAL
TO SELECT BOOT ROM;
1 = ADDRESSING MODE 1
INTERRUPT LATCH
READ ONLY;
DISABLE STATUS
READ ONLY; INTERRUPT
ARCE; ASIC READ CYCLE EXTEND
WHEN SET EXTENDS CYCLE ON
EXTERNAL ASIC READS
RESERVED (NOTE)
CR
8
5
6
7
0
1
2
3
4
9
5 4 3 2 1 0
NOTE: Always read as ‘‘0’’. Should be set = 0 during Write operations.
FIGURE 11.
BIT ASSIGNMENTS
CR
PC
I
I
TOP
I
I
I
MD
TOP
EXT
MD
SR
SR
TC0
TC1
TC2
TP0
TP1
TP2
MHR
IBC
MLR
MXR
IVR
ALL ZEROS
VECTOR ADDRESS
(SEE TABLE 1)
0
1
IBC
2
3
4
5
6
7
11
8
9
10
12
13
14
15
IVR
BIT 10
BIT 11
BIT 12
BIT 15
BIT 14
BIT 13
IBC
IBC
IBC
IBC
IBC
IBC
MA15-MA00
FIGURE 12.
BIT ASSIGNMENTS
IVR
IBC
HS-RTX2010RH
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