24
Step Arithmetic instructions which are performed through the
ALU are divide and square root. Execution of each step of the
arithmetic operation takes one cycle, a 32/16-bit Step Divide
takes 21 cycles, and a 32/16-bit Step Square Root takes 25
cycles. Sign and scaling functions are controlled by the ALU
function and shift options, which are part of the coded
instruction contained in
. See Table 20 and Table 21
and the Programmer’s Reference Manual for details.
Unsigned Step Divide operation assumes a double precision
(32-bit) dividend, with the most significant word placed in
, the less significant word in
. In each step, if the contents in
greater than the contents in
is generated), then the contents of
from the contents of
. The result of the subtraction is
placed into
. The contents of
then jointly shifted left one bit (32-bit left shift), where the
value shifted into the least significant bit of
of the Borrow bit on the first pass, or the value of the
Complex Carry bit on each of the subsequent passes. On
the 15th and final pass, only
the value of the Complex Carry bit into the LSB.
shifted. The final result leaves the quotient in
remainder in
.
TOP
, and the divisor in
are equal to or
(and therefore no borrow
are subtracted
MD
and
are
is the value
is shifted left, receiving
NEXT
is not
, and the
During a Step Square Root operation, the 32-bit argument is
assumed to be in
and
operation. The first step begins with
The Step Square Root is performed much like the Step
Divide, except that the input from the Y-bus is the logical OR
of the contents of
and the value in
SR
, as in the Step Divide
containing zeros.
MD
shifted one
place to the left (2*
performed,
one place to the right. At the end of the operation, the square
root of the original value is in
remainder is in
.
TOP
). When the subtraction is
is OR’ed into
MD
, and
is shifted
and
, and the
HS-RTX2010RH Floating Point/DSP On
Chip Peripherals
The HS-RTX2010RH Multiplier-Accumulator
The Hardware Multiplier-Accumulator (MAC) on the
HS-RTX2010RH functions as both a Multiplier, and a
Multiplier- Accumulator. When used as a Multiplier alone, it
multiplies two 16-bit numbers, yielding a 32-bit product in
one clock cycle. When used as a Multiplier-Accumulator, it
multiplies two 16-bit numbers, yielding an intermediate 32-bit
product, which is then added to the 48-bit Accumulator. This
entire process takes place in a single clock cycle.
The Multiplier-Accumulator functions are activated by I\O
Read and Write instructions to ASIC Bus addresses
assigned to the MAC.
The MAC’s input operands come from three possible
sources (see Figure 25):
1. The
2. The Parameter (Data) Stack and memory via
(Streamed mode only - see the Programmer’s Reference
Manual).
3. Memory via
and an input from the ASIC Bus
(Streamed mode only - see the Programmer’s Reference
Manual).
and
registers.
OPERAND
(A)
Y
T-BUS
ALU
PROGRAM
MEMORY
SELECT
OPERAND (B)
TOP
SHIFTER
ALU
CONTROL
Y
T
5 LEAST
SIGNIFICANT
BITS
ASIC BUS
DEVICE
INTERNAL
REGISTERS
NEXT
DECODE
I R
I R
NOTE: Data Paths are represented by solid lines; Control Paths are represented by dashed lines.
FIGURE 24. ALU OPERATIONS-CONTROL PATHS AND DATA FLOW
IR
TOP
MD
NEXT
TOP
MD
TOP
TOP
TOP
NEXT
NEXT
TOP
EXT
TOP
NEXT
MD
MD
SR
SR
MD
NEXT
TOP
EXT
NEXT
EXT
HS-RTX2010RH