參數(shù)資料
型號： HS8-RTX2010RH-8
廠商： INTERSIL CORP
元件分類： 微控制器/微處理器
英文描述： Radiation Hardened Real Time Express⑩ Microcontroller
中文描述： 16-BIT, 8 MHz, MICROCONTROLLER, CPGA85
封裝： PGA-85
文件頁數(shù)： 22/36頁
文件大?。?/td> 406K
代理商： HS8-RTX2010RH-8
22
During read and write operations to the Configuration
Register, (
), interrupts are inhibited to allow the program
to save and restore the state of the Interrupt Enable bit.
In addition to disabling interrupts at the processor level, all
interrupts except the Non-Maskable Interrupt (NMI) can be
individually masked by the Interrupt Controller by setting the
appropriate bit in the Interrupt Mask Register (
Resetting the HS-RTX2010RH causes all bits in the
be cleared, thereby unmasking all interrupts.
).
IMR
to
The NMI on the HS-RTX2010RH has two modes of operation
which are controlled by the NMI_MODE Flag (bit 11 of the
). When this bit is cleared (0), the NMI can not be
masked, and can interrupt any cycle. This allows a fast
response to the NMI, but may not allow a return from interrupt
to operate correctly. NMI_MODE is cleared when the
processor is Reset. When NMI_MODE is set (1), a return
from the NMI service routine will result in the processor
continuing execution in the state it was in when it was
interrupted. When in this second mode NMI may be inhibited
by the processor during certain critical operations (see
Interrupt Suppression), and may, therefore, not be serviced as
quickly as in the first mode of operation. When servicing an
NMI_MODE set to 1, further NMIs and maskable interrupts
are disabled until the NMI Interrupt Service Routine has
completed, and a return from interrupt has been executed.
The Interrupt Controller prioritizes interrupt requests and
generates an Interrupt Vector for the highest priority interrupt
request. The address that the vector points to is determined
by the source of the interrupt and the contents of the
Interrupt Base/Control Register (
the Interrupt Vector Register bit assignments. Because
address bits MA19-MA16 are always zero in an Interrupt
). See Figure 12 for
Acknowledge cycle, the entry point to the Interrupt Handlers
must reside on Memory Page zero.
Because address bits MA04-MA01 are always zero in an
Interrupt Acknowledge cycle, Interrupt Vectors are 32 bytes
apart. This means that Interrupt Handler routines that are 32
bytes or less can be compiled directly into the Interrupt
Table. Interrupt Handlers greater than 32 bytes must be
compiled separately and called from the Interrupt Table.
The rest of the vector is generated as indicated in Table 1. To
guarantee that the Interrupt Vector will be stable during an
INTA cycle, the Interrupt Controller inhibits the generation of a
new Interrupt Vector while INTA is high, and will not begin
generating a new Interrupt Vector on either edge of INTA.
The Interrupt Vector can also be read from the Interrupt
Vector Register (
) directly. This allows interrupt
requests to be monitored by software, even if they are
disabled by the processor. If no interrupts are being
requested, bit 09 of the
IVR
will be 1.
External interrupts EI5-EI1 are active HIGH level-sensitive
inputs. (Note: When used as Timer/Counter inputs, EI5-EI3
are edge sensitive). Therefore, the Interrupt Handlers for
these interrupts must clear the source of interrupt prior to
returning to the interrupted code. The external NMI,
however, is an edge-sensitive input which requires a rising
edge to request an interrupt. The NMI input also has a glitch
filter circuit which requires that the signal that initiates the NMI
must last at least two rising and two falling edges of ICLK.
Finally, a mechanism is provided by which an interrupt can
be requested by using a software command. The Software
Interrupt (SWI) is requested by executing an instruction that
will set an internal flip-flop attached to one input of the
TABLE 4. INTERRUPT SOURCES, PRIORITIES AND VECTORS
PRIORITY
INTERRUPT SOURCE
SENSITIVITY
BIT
VECTOR ADDRESS BITS
09
08
07
06
05
0 (High)
NMI
Non-Maskable Interrupt
Pos Edge
N/A
0
1
1
1
1
1
EI1
External Interrupt 1
High Level
01
0
1
1
1
0
2
PSU
Parameter Stack Underflow
High Level
02
0
1
1
0
1
3
RSU
Return Stack Underflow
High Level
03
0
1
1
0
0
4
PSV
Parameter Stack Overflow
High Level
04
0
1
0
1
1
5
RSV
Return Stack Overflow
High Level
05
0
1
0
1
0
6
EI2
External Interrupt 2
High Level
06
0
1
0
0
1
7
TCI0
Timer/Counter 0
Edge
07
0
1
0
0
0
8
TCI1
Timer/Counter 1
Edge
08
0
0
1
1
1
9
TCI2
Timer/Counter 2
Edge
09
0
0
1
1
0
10
EI3
External Interrupt 3
High Level
10
0
0
1
0
1
11
EI4
External Interrupt 4
High Level
11
0
0
1
0
0
12
EI5
External Interrupt 5
High Level
12
0
0
0
1
1
13 (Low)
SWI
Software Interrupt
High Level
13
0
0
0
1
0
N/A
None
No Interrupt
N/A
N/A
1
0
0
0
0
IMR
CR
IMR
CR
IBC
IVR
HS-RTX2010RH
相關(guān)PDF資料
PDF描述
HS9-RTX2010RH-8 Radiation Hardened Real Time Express⑩ Microcontroller
HS-RTX2010RH Radiation Hardened Real Time Express⑩ Microcontroller
HS8-RTX2010RH Radiation Hardened Real Time Express⑩ Microcontroller
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HS8-RTX2010RH-Q 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Real Time Express⑩ Microcontroller
HS-8T 制造商:MG Electronics 功能描述:8'' Aluminum Weatherproof PA Horn
HS8V 制造商:Apex Tool Group 功能描述:1/4 IN. X 3 1/8 IN. FULL HOLLOW SHAFT NUTDRIVER, RED HANDLE, CARDED 制造商:CASIO 功能描述:CALCULATOR 8 DIGIT 制造商:CASIO 功能描述:CALCULATOR, 8 DIGIT 制造商:Xcelite 功能描述:1/4in x 3-1/8in Full Hollow Shaft Nutdriver 制造商:Xcelite 功能描述:Xcelite 1/4 X 3 1/8 Full Hollow Shaft NutDriver, Red Handle, Carded
HS-8V-W1 制造商:Black Box Corporation 功能描述:1 year warranty for HS-8V
HS-8V-W3 制造商:Black Box Corporation 功能描述:3 year warranty for HS-8V
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