參數(shù)資料
型號(hào): HS1-3182-9
廠(chǎng)商: INTERSIL CORP
元件分類(lèi): Line Driver or Receiver
英文描述: LINE DRIVER, CDIP16
封裝: SIDE BRAZED, DIP-16
文件頁(yè)數(shù): 2/5頁(yè)
文件大?。?/td> 113K
代理商: HS1-3182-9
179
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Block Diagram
Typical Application
NOTE: The rise and fall time of the outputs are set to ARINC specified values by CA and CB. Typical CA = CB = 75pF for high speed and
300pF for low speed operation. The output HI and low levels are set to ARINC specifications by VREF.
LEVEL SHIFTER
AND SLOPE
CONTROL (A)
LEVEL SHIFTER
AND SLOPE
CONTROL (B)
CURRENT
REGULATOR
DATA (A)
CLOCK
VREF
SYNC
DATA (B)
V1
(4)
(14)
(1)
(3)
(13)
(16)
(2)
(9) (5)
+V CA
OUTPUT
DRIVER
(A)
ROUT/2
OUTPUT
DRIVER
(B)
GND
(8)
-V
CB
(7)
(12)
OVER-VOLTAGE
PROTECTION
FA
FB
CL
AOUT
BOUT
RL
(6)
(11)
HS-3182
ARINC DRIVER
CIRCUIT
16 LEAD DIP
GND
-V
DATA (B)
DATA (A)
SYNC
CLOCK
V1 VREF
CA
CB
+V
AOUT
BOUT
TO BUS
(SEE
NOTE)
PIN NUMBER 10, 15 = NC
-15V
(7)
(8)
(2)
(9)
+15V
CA
CB
(12)
(5)
+5V
(1)
(16)
(14)
(3)
PIN NUMBERS INDICATED BY ( )
HS-3282
CMOS ARINC
CIRCUIT
429D0
31
32
(4)
(13)
HS-3182
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