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參數(shù)資料
| 型號： | HPC3130PBMQUADFLAT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PCI HOT PLUG CONTROLLER |
| 中文描述： | 的PCI熱插拔控制器 |
| 文件頁數(shù)： | 30/40頁 |
| 文件大小： | 555K |
| 代理商： | HPC3130PBMQUADFLAT |
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HPC3130
PCI HOT PLUG CONTROLLER
SCPS029B – DECEMBER1998
30
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
interrupt event status register
Bit
7
6
5
4
3
2
1
0
Name
Interrupt event status register
Type
R
R/C
R/C
R/C
R/C
R/C
R/C
R/C
Default
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
Default:
Description:
Interrupt event status
Read-only, Read/Clear
06h (slot 0), 0Eh (slot 1), 16h (slot 2), 1Eh (slot 3)
00h
This register reads interrupt status, and clears the interrupt. All functional bits in this
register are readable and cleared by a write back of 1. The HPC3130 can be programmed
to generate an interrupt, signaled through the open-drain INTR, after detecting various
events. Each event is individually enabled through the interrupt event enable register.
Table 12. Interrupt Event Status Register
BIT
TYPE
NAME
FUNCTION
7
R
RSVD
Reserved. This bit returns 0 when read.
6
R/C
BUS_S
PCI Bus CBT switch status. This bit is set when the BUSON output is asserted, and is cleared by a write
back of 1. The BUS event is intended for use with the idling protocol.
5
R/C
PWRGOOD_S
Power good status. This bit is set when the PWRGOOD input changes state.
4
R/C
PWRFAULT_S
Power fault status. This bit is set when the PWRFAULT input is asserted.
3
R/C
DETECT1_S
Mechanical detect 1 status. This bit is set when the DETECT1 input changes state.
2
R/C
DETECT0_S
Mechanical detect 0 status. This bit is set when the DETECT0 input changes state.
1
R/C
PRSNT2_S
Card present 2 status. This bit is set when the PRSNT2 input changes state.
0
R/C
PRSNT1_S
Card present 1 status. This bit is set when the PRSNT1 input changes state.
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相關(guān)代理商/技術(shù)參數(shù) |
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| HPC3130PGE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bus Interface/Controller |
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| HPC36003L30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microcontroller |
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