HPC3130
PCI HOT PLUG CONTROLLER
SCPS029B – DECEMBER1998
26
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
general configuration register
Bit
7
6
5
4
3
2
1
0
Name
General configuration register
Type
R
R
R
R
R/W
R/W
R
R/W
Default
0
0
0
1
0
0
X
0
Register:
Type:
Offset:
Default:
Description:
General configuration
Read-only, Read/Write
00h (slot 0), 08h (slot 1), 10h (slot 2), 18h (slot 3)
0Xh
This register is for general configurations and indications. The automatic PCI bus
connection sequencing is enabled through this register, and the register access mode is
indicated. This register is shared among all four slots.
Table 8. General Configuration Register
BIT
TYPE
NAME
FUNCTION
7–4
R
RSVD
Reserved for revision ID. These bits return 0001 for this device.
3–2
R/W
SEQUENCING
Automatic PCI bus connection sequencing. These bits control the sequencing used to connect the hot-
plug slot to the PCI bus.
00 = Manual sequencing through register accesses
01 = Auto–Sequence 1: Enable CBT switches before deasserting RST
10 = Auto–Sequence 2: Enable CBT switches after deasserting RST
11 = Reserved
1
R
SYSM66STAT
Status of SYSM66EN. This bit represents the latched value of SYSM66EN during a PCI reset. A value of
1 indicates the PCI bus is operating at a frequency greater than 33 MHz. A value of 0 indicates the PCI
bus is operating at 33 MHz or less.
0
R/W
PROTECTEN
Protection enable. This bit enables a protection mechanism provided by the HPC3130. When this bit is
enabled and either of the DETECT[1:0] inputs are high, the HPC3130 drives the BUS_ON and CLKON
outputs high. The HPC3130 also drives PWRON/OFF and REQ64ON outputs low.