參數(shù)資料
型號： HPC3130PBKLOW-PROFILEQUAD
廠商： Texas Instruments, Inc.
英文描述： PCI HOT PLUG CONTROLLER
中文描述： 的PCI熱插拔控制器
文件頁數(shù)： 12/40頁
文件大?。?/td> 555K
代理商： HPC3130PBKLOW-PROFILEQUAD
HPC3130
PCI HOT PLUG CONTROLLER
SCPS029B – DECEMBER1998
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
This section describes the HPC3130 terminal functions. The terminals are grouped in tables by function.
power supply terminal functions
TERMINAL
NAME
NO.
120
NO.
128
NO.
144
I/O
FUNCTION
GND
11, 17, 26, 41, 51,
68, 79, 101, 112, 117
12, 18, 27, 44, 54,
73, 84, 108, 119, 124
14, 20, 29, 50, 60,
83, 94, 122, 133, 138
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Device ground terminals
VCC
VCC5V
VCCP
6, 36, 56, 85, 95
7, 39, 59, 90, 102
9, 45, 65, 100, 116
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3.3
-
V power supply
5
-
V clamp
-
rail voltage supply
Clamp rail voltage for PCI signaling (5V or 3.3V)
15, 28, 46, 74, 107
16, 29, 49, 79, 114
18, 32, 55, 89, 128
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22
23
25
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control bus interface
TERMINAL
NAME
NO.
120
NO.
128
NO.
144
I/O
FUNCTION
A2/ADD2
A1/ADD1
A0/ADD0
48
49
50
51
52
53
57
58
59
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Parallel bus address. These terminals are address inputs in generic parallel bus cycles and are
only used when the SMODE is input low. These lower address terminals select one of the eight
registers for read/write access.
Serial bus address select. These terminals indicate the full serial bus address of the HPC3130
when the SMODE is input high.
A4/ADD4
A3/ADD3
45
47
48
50
54
56
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Parallel bus address. These terminals are address inputs in generic parallel bus cycles, and are
only used when SMODE is input low. These upper address terminals select one of four hot-plug
slots supported by the HPC3130.
Serial bus address select. These terminals indicate the full serial bus address of the HPC3130
when the SMODE is input high.
CS
34
37
43
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Chip selection. This active low input selects the HPC3130 chip as addressed in the current
generic parallel bus cycle. This chip input is only valid if the SMODE is input low. Multiple
HPC3130 chips may exist in a system with external logic driving this signal.
DATA1/ADD6
DATA0/ADD5
43
44
46
47
52
53
I/O
Parallel bus data. This bus is the data bus in generic parallel bus cycles and is selected when the
SMODE is input low. The data path is used during both read and write transactions to internal
registers when the parallel control bus interface is implemented.
Serial bus address selection. These terminals indicate the full serial bus address of the
HPC3130 when the SMODE is input high.
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
35
37
38
39
40
42
38
40
41
42
43
45
44
46
47
48
49
51
I/O
Parallel bus data. This bus is the data bus in generic parallel bus cycles and is selected when the
SMODE is input low. The data path is used during both read and write transactions to internal
registers when the parallel control bus interface is implemented.
RD/SDA
29
30
34
I/O
Read selection. This terminal indicates a register read cycle when the SMODE input is low and
the CS terminal input is asserted. This is used to read an internal HPC3130 register.
Serial bus data. This terminal signals the serial bus data when the SMODE input is high. It is used
during internal register read and write transactions.
Write selection. This terminal indicates a register write cycle when the SMODE input is low and
the CS terminal input is asserted. This input is used to write to an internal HPC3130 register.
Serial bus clock. This terminal inputs serial bus clock in when the SMODE input is high. It is used
during internal register read and write transactions.
WR/SCL
30
31
36
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