參數(shù)資料
型號(hào)： HPC3130APBKLOW-PROFILEQUA
廠商： Texas Instruments, Inc.
英文描述： DIODE ZENER DUAL COMMON-CATHODE 300mW 33Vz 5mA-Izt 0.0606 0.1uA-Ir 25 SOT-23 3K/REEL
中文描述： 的PCI熱插拔控制器
文件頁(yè)數(shù)： 17/41頁(yè)
文件大?。?/td> 537K
代理商： HPC3130APBKLOW-PROFILEQUA
HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
SDA
SCL
Start Condition
Stop Condition
Change of
Data Allowed
Data Line Stable, Data Valid
Figure 2. Serial Bus Start/Stop Conditions and Bit Transfers
Data is transferred on the bus in 8-bit bytes. The number of bytes that can be transmitted during a data transfer
is unlimited; however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is
indicated by the receiver pulling down the SDA signal so that it remains low during the high state of the SCL
signal as shown in Figure 3.
SCL From
Master
1
2
3
7
8
9
SDA Output
By Transmitter
SDA Output
By Receiver
Figure 3. Serial Bus Protocol – Acknowledge
The HPC3130A serial bus slave interface protocol for write transactions is illustrated in Figure 4. The R/W
command bit is set to zero to indicate a write transaction. For a write operation, the HPC3130A requires a word
address field after the slave address. This address field is comprised of eight bits. Upon receipt of the word
address, the HPC3130A responds with an acknowledge, and waits for the next eight bits of data, again
responding with an acknowledge. After all the data bytes are transferred, the master then terminates the transfer
by generating a STOP condition. The device automatically increments the address for subsequent data words.
After the receipt of each word, the low order address bits are internally incremented by one.
S
b6
b4
b5
b3 b2
b1 b0
0
b7 b6 b5 b4 b3
b2 b1
b0
A
A
Slave Address
Word Address
R/W
S/P = Start/stop condition
A = Slave acknowledgment
b7 b6
b4
b5
b3
b2 b1 b0
A
P
Data Byte
Figure 4. Serial Bus Protocol – Byte Write
A byte read operation is illustrated in Figure 5. The read protocol is very similar to the write protocol, except the
R/W command bit must be set to one to indicate a read data transfer. First the master issues a write command
that includes the START condition and the slave address field (with the R/W bit set to write), followed by the
address of the word it is to read. This procedure sets the internal address counter of the HPC3130A to the
desired address. After the word address acknowledgment is received by the master, the master immediately
reissues a START condition followed by another slave address field with the R/W bit set to read. The HPC3130A
responds with an acknowledgment and transmits the eight data bits stored in the addressed location. If the
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