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參數(shù)資料
| 型號： | HPC16003 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | High-Performance microControllers |
| 中文描述： | 高性能微控制器 |
| 文件頁數(shù)： | 11/36頁 |
| 文件大小： | 467K |
| 代理商： | HPC16003 |
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AC Electrical Specifications
Test Conditions V
CC
e
4.5V and 5.5V (Unless Otherwise Specified) (Note 1)
(Continued)
Symbol
Parameter
Conditions
SBGRP 9
a
25
§
C
SBGRP 10
a
125
§
C
SBGRP 11
b
55
§
C
Units
Notes
Min
Max
Min
Max
Min
Max
t
RWP
e
t
C
RDY Pulse Width
100
100
100
ns
(Note 6)
t
SALE
e
*/4
t
C
a
40
Falling Edge of HLD to
to Rising Edge of ALE
115
115
115
ns
(Note 6)
t
HWP
e
t
C
a
10
HLD Pulse Width
110
110
110
ns
(Note 6)
t
HAD
e
*/4
t
C
a
85
Rising Edge on HLD to
Rising Edge on HLDA
160
160
160
ns
(Note 6)
t
HAE
e
t
C
a
100
Falling Edge on HLD to
Falling Edge on HLDA
200
200
200
ns
(Note 6)
t
BF
e
(/2
t
C
a
66
BUS Float before
Falling Edge on HLDA
116
116
116
ns
(Note 6)
t
BE
e
(/2
t
C
a
66
BUS Enable from
Rising Edge of HLDA
116
116
116
ns
(Note 6)
t
UAS
Address Setup Time to
Falling Edge of URD
10
10
10
ns
(Note 6)
t
UAH
Address Hold Time from
Rising Edge of URD
10
10
10
ns
(Note 6)
t
RPW
URD Pulse Width
100
100
100
ns
(Note 6)
t
OE
URD Falling Edge to
Data Out Valid
60
60
60
ns
(Note 6)
t
RDRDY
RDY Delay from
Rising Edge of URD
70
70
70
ns
(Note 6)
t
WDW
UWR Pulse Width
40
40
40
ns
(Note 6)
t
UDS
Data Invalid before
Trailing Edge of UWR
10
10
10
ns
(Note 6)
t
UDH
Data In Hold after
Rising Edge of UWR
15
15
15
ns
(Note 6)
t
A
WRRDY Delay from
Rising Edge of UWR
70
70
70
ns
(Note 6)
Note 1:
Electrical end point testing (when required) for groups C & D shall consist only of subgroups 1, 2, 9 and 10.
Note 5:
Tested in functional patterns. Not directly measured.
Note 6:
C
L
e
70 pF. Input and output levels are per DC characteristics.
Pin Descriptions
The HPC16083 is available in 68-pin PLCC, LDCC, PGA,
and 80-pin PQFP packages.
I/O PORTS
Port A is a 16-bit bidirectional I/O port with a data direction
register to enable each separate pin to be individually de-
fined as an input or output. When accessing external memo-
ry, port A is used as the multiplexed address/data bus.
Port B is a 16-bit port with 12 bits of bidirectional I/O similar
in structure to Port A. Pins B10, B11, B12 and B15 are gen-
eral purpose outputs only in this mode. Port B may also be
configured via a 16-bit function register BFUN to individually
allow each pin to have an alternate function.
B0:
B1:
B2:
B3:
B4:
B5:
B6:
B7:
B8:
B9:
B10: UA0
B11: WRRDY Write Ready Output for UPI Mode
B12:
B13: TS2
Timer Synchronous Output
TDX
UART Data Output
CKX
T2IO
T3IO
SO
SK
HLDA
TS0
TS1
UART Clock (Input or Output)
Timer2 I/O Pin
Timer3 I/O Pin
MICROWIRE/PLUS Output
MICROWIRE/PLUS Clock (Input or Output)
Hold Acknowledge Output
Timer Synchronous Output
Timer Synchronous Output
Address 0 Input for UPI Mode
11
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