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| 型號： | HPC-DEV-SYS2 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | High-Performance Communications MicroController |
| 中文描述： | 高性能通信微控制器 |
| 文件頁數(shù)： | 19/30頁 |
| 文件大?。?/td> | 362K |
| 代理商： | HPC-DEV-SYS2 |
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HDLC Functional
Description
(Continued)
the user selects the error checking code to be used through
software control (HDLC control reg). The two error checking
polynomials available are:
(1) CRC-16 (x
16
a
x
15
a
x
2
a
1)
(2) CCITT CRC (x
16
a
x
12
a
x
5
a
1)
SYNCHRONOUS BYPASS MODE
When the BYPAS bit is set in the HDLC control register, all
HDLC framing/formatting functions for the specified HDLC
channel are disabled.
This allows byte-oriented data to be transmitted and re-
ceived synchronously thus ‘‘bypassing’’ the HDLC func-
tions.
LOOP BACK OPERATIONAL MODE
The user has the ability, by setting the appropriate bit in the
register to internally route the transmitter output to the re-
ceiver input, and to internally route the RX pin to the TX pin.
DMA Controller
GENERAL INFORMATION
The HPC46400E uses Direct Memory Access (DMA) logic
to facilitate data transfer between the 2 full Duplex HDLC
channels and external packet RAM. There are four DMA
channels to support the four individual HDLC channels.
Control of the DMA channels is accomplished through regis-
ters which are configured by the CPU. These control regis-
ters define specific operation of each channel and changes
are immediately reflected in DMA operation. In addition to
individual control registers, global control bits (MSS and
MSSC in Message Control Register) are available so that
the HDLC channels may be globally controlled.
The DMA issues a bus request to the CPU when one or
more of the individual HDLC channels request service.
Upon receiving a bus acknowledge from the CPU, the DMA
completes all requests pending and any requests that may
have occurred during DMA operation before returning con-
trol to the CPU. If no further DMA transfers are pending, the
DMA relinquishes the bus and the CPU can again initiate a
bus cycle.
Four memory expansion bits have been added for each of
the four channels to support data transfers into the expand-
ed memory bank areas.
The DMA has priority logic for servicing DMA requests. The
priorities are:
1st priority àààààààààààààààààààReceiver channel 1
2nd priority àààààààààààààààààààTransmit channel 1
3rd priority ààààààààààààààààààààReceive channel 2
4th priority àààààààààààààààààààTransmit channel 2
RECEIVER DMA OPERATION
The receiver DMA consists of a shift register and two buff-
ers. A receiver DMA operation is initiated by the buffer regis-
ters. Once a byte has been placed in a buffer register from
the HDLC, it generates a request and upon obtaining control
of the bus, the DMA places the byte in external memory.
RECEIVER REGISTERS
All the following registers are Read/Write
A. Frame Length Register
This user programmable 16-bit register contains the max-
imum number of bytes to be placed in a data ‘‘block’’. If
this number is exceeded, a Frame Too Long error is gener-
ated. DMA is stopped to prevent memory from being over-
written, however the receiver continues until the closing flag
is received in order to check the CRC.
B. CNTRL ADDR 1
For
CNTRL ADDR register contains the
external memory address where
the Frame Header (Control & Ad-
dress fields) are to be stored and
the DATA ADDR register contains
an equivalent address for the Infor-
mation field.
split
frame
operation,
the
DATA ADDR 1
CNTRL ADDR 2
DATA ADDR 2
For non-split frame operation, the
CNTRL and DATA ADDR registers
each contain the external memory
address for entire frames.
TRANSMITTER DMA OPERATION
The transmitter DMA consists of a shift register and two
buffers. A transmitter DMA cycle is initiated by the TX data
buffers. The TX data buffers generate a request when either
one is empty and the DMA responds by placing a byte in the
buffer. The HDLC transmitter can then accept the byte to
send when needed, upon which the DMA will issue another
request, resulting in a subsequent DMA cycle.
TRANSMITTER REGISTERS
The following registers are Read/Write:
FIELD ADDRESS 1
Field Address 1 and Field Address
2 are starting addresses of blocks
of information to be transmitted.
BYTE COUNT 1
FIELD ADDRESS 2
Byte Count 1 and Byte Count 2 are
the number of bytes in the block to
be transmitted.
BYTE COUNT 2
Shared Memory Support
Shared memory access provides a rapid technique to ex-
change data. It is effective when data is moved from a pe-
ripheral to memory or when data is moved between blocks
of memory. A related area where shared memory access
proves effective is in multiprocessing applications where
two CPUs share a common memory block. The HPC46400E
supports shared memory access with two pins. The pins are
the RDY/HLD input pin and the HLDA output pin. The user
can software select either the Hold or Ready function on the
RDY/HLD pin by the state of a control bit. The HLDA output
must be selected as the HLDA output on pin B7 by soft-
ware.
The host uses DMA to interface with the HPC46400E. The
host initiates a data transfer by activating the HLD input of
the HPC46400E. In response, the HPC46400E places its
system bus in a TRI-STATE Mode, freeing it for use by the
host. The host waits for the acknowledge signal (HLDA)
from the HPC46400E indicating that the sytem bus is free.
On receiving the acknowledge, the host can rapidly transfer
data into, or out of, the shared memory by using a conven-
tional DMA controller. Upon completion of the message
transfer, the host removes the HOLD request and the
HPC46400E resumes normal operations. See Figure 18
(HPC46400E shared Memory Using HOLD).
An alternate approach is to use the Ready function avail-
able on either the RDY/HLD pin or the INT4/RDY pin. See
Figure 19 (HPC46400E Shared Memory Using READY).
This technique is often required when the HPC is sharing
memory over a system backplane bus.
19
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