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| 型號： | HPC-DEV-SYS2 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | High-Performance Communications MicroController |
| 中文描述： | 高性能通信微控制器 |
| 文件頁數(shù)： | 15/30頁 |
| 文件大?。?/td> | 362K |
| 代理商： | HPC-DEV-SYS2 |
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Timer Overview
(Continued)
The timers T1 through T3 in conjunction with their registers
form Timer-Register pairs. The registers hold the pulse du-
ration values. All the Timer-Register pairs can be read from
or written to. Each timer can be started or stopped under
software control. Once enabled, the timers count down, and
upon underflow, the contents of its associated register are
automatically loaded into the timer.
SYNCHRONOUS OUTPUTS
The flexible timer structure of the HPC46400E simplifies
pulse generation and measurement. There are four syn-
chronous timer outputs (TS0 through TS3) that work in con-
junction with the timer T2. The synchronous timer outputs
can be used either as regular outputs or individually pro-
grammed to toggle on timer T2 underflows (see Figure 12).
Maximum output frequency for any timer output can be ob-
tained by setting timer/register pair to zero. This then will
produce an output frequency equal to
(/2
the frequency of
the source used for clocking the timer.
Timer Registers
There are four control registers that program the timers. The
divide by (DIVBY) register programs the clock input to tim-
ers T2 and T3. The timer mode register (TMMODE) contains
control bits to start and stop timers T1 through T3. It also
contains bits to latch, acknowledge and enable interrupts
from timers T0 through T3.
Timer Applications
The use of Pulse Width Timers for the generation of various
waveforms is easily accomplished by the HPC46400E.
Frequencies can be generated by using the timer/register
pairs. A square wave is generated when the register value is
a constant. The duty cycle can be controlled simply by
changing the register value.
TL/DD/10422–22
FIGURE 13. Square Wave Frequency Generation
Synchronous outputs based on Timer T2 can be generated
on the 4 outputs TS0–TS3. Each output can be individually
programmed to toggle on T2 underflow. Register R2 con-
tains the time delay between events. Figure 14 is an exam-
ple of synchronous pulse train generation.
TL/DD/10422–23
FIGURE 14. Synchronous Pulse Generation
WATCHDOG Logic
The WATCHDOG Logic monitors the operations taking
place and signals upon the occurrence of any illegal activity.
The illegal conditions that trigger the WATCHDOG logic are
potentially infinite loops. Should the WATCHDOG register
not be written to before Timer T0 overflows twice, or more
often than once every 4096 counts, an infinite loop condi-
tion is assumed to have occurred. The illegal condition
forces the Watch Out (WO) pin low. The WO pin is an open
drain output and can be connected to the RESET or NMI
inputs or to the users external logic.
MICROWIRE/PLUS
MICROWIRE/PLUS is used for synchronous serial data
communications (see Figure 15). MICROWIRE/PLUS has
an 8-bit parallel-loaded, serial shift register using SI as the
input and SO as the output. SK is the clock for the serial
shift register (SIO). The SK clock signal can be provided by
an internal or external source. The internal clock rate is pro-
grammable by the DIVBY register. A DONE flag indicates
when the data shift is completed.
The MICROWIRE/PLUS capability enables it to interface
with any of National Semiconductor’s MICROWIRE periph-
erals (i.e., ISDN Transceivers, A/D converters, display driv-
ers, EEPROMs).
TL/DD/10422–24
FIGURE 15. MICROWIRE/PLUS
15
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|---|---|
| HPC-DEV-SYS2-E | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High-Performance Communications MicroController |
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| HPC-DEV-SYS4-E | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High-Performance microController with A/D |
| HPC-DEV-WDBC | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High-Performance Communications MicroController |
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