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| 型號： | HMS99C58S |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8-BIT SINGLE-CHIP MICROCONTROLLERS WITH EMBEDDED FLASH |
| 中文描述： | 8位單片機與嵌入式閃存微控制器 |
| 文件頁數(shù)： | 51/73頁 |
| 文件大小： | 696K |
| 代理商： | HMS99C58S |
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HMS99C51S/52S/54S/56S/58S
Sep. 2004 Ver 1.01
47
Flash Memory Lock Bits
The three lock bits provide different levels of protection for the on-chip code and data, when programmed as
shown in Table 14.
Note:
U : unprogrammed or “1”, P : programmed or “0”, X: don’t care
Note:
Security level 2 and 3 should only be programmed after Flash and code verification.
These security bits protect the code access through the parallel programming interface. They are set by default
to level 1. Though at level 2, 3 and 4, the code access through the ISP is still possible.
Default Values
The default value of the HSB provides parts ready to be programmed with ISP
BLJB_EN: BLJB bit is enabled or disabled.(default : disabled)
BLJB: Programmed force ISP operation(Default : ISP inactivated)).
LB2-0: Security level four to protect the code from a parallel access with maximum
security.(Default : Level 1)
Software Security
The software security provide two different levels of protection for the on-chip code and data,
Level 1 : No program lock features enabled.
Level 2 : ISP programming and verify of the Flash is disabled.
Program Lock Bit
Protection Description
Security
Level
LB0
LB1
LB2
1
U
U
U
No program lock features enabled.
2
P
U
U
MOVC instruction executed from external program
memory is disabled from fetching code bytes from
internal memory, EA is sampled and latched on reset,
and further parallel programming of the Flash is disabled.
ISP and software programming with ISP are still allowed.
3
X
P
U
Same as 2, also verify through parallel programming
interface is disabled.
4
X
X
P
Same as 3, also external execution is disable.
Table 14. Program Lock Bits
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