參數(shù)資料
型號(hào): HMS81C2020AQ
廠商: Electronic Theatre Controls, Inc.
英文描述: CMOS Single-Chip 8-Bit Microcontroller with A/D Converter & VFD Driver
中文描述: CMOS單芯片8位微控制器與A / D轉(zhuǎn)換器
文件頁(yè)數(shù): 77/107頁(yè)
文件大?。?/td> 1482K
代理商: HMS81C2020AQ
HMS81C2012A/2020A
SEP. 2004 Ver 2.00
73
16.4 External Interrupt
The external interrupt on INT0 and INT1 pins are edge
triggered depending on the edge selection register IEDS
(address 0F8
H
) as shown in Figure 16-7.
The edge detection of external interrupt has three transition
activated mode: rising edge, falling edge, and both edge.
Figure 16-7 External Interrupt Block Diagram
INT0 and INT1 are multiplexed with general I/O ports
(R00 and R01). To use as an external interrupt pin, the bit
of R4 port mode register R0FUNC should be set to “1” cor-
respondingly.
Example:
To use as an INT0 and INT1
:
:
;
**** Set port as an input port R00,R01
LDM
;
;
**** Set port as an interrupt port
LDM
;
;
**** Set Falling-edge Detection
LDM
:
:
:
R0IO,#1111_1100B
R0FUNC,#0000_0011B
IEDS,#0000_0101B
Response Time
The INT0 and INT1 edge are latched into INT0IF and
INT1IF at every machine cycle. The values are not actually
polled by the circuitry until the next machine cycle. If a re-
quest is active and conditions are right for it to be acknowl-
edged, a hardware subroutine call to the requested service
routine will be the next instruction to be executed. The
DIV itself takes twelve cycles. Thus, a minimum of twelve
complete machine cycles elapse between activation of an
external interrupt request and the beginning of execution
of the first instruction of the service routine.
Figure 16-8shows interrupt response timings.
Figure 16-8 Interrupt Response Timing Diagram
INT1IF
INT1 pin
INT1 INTERRUPT
IEDS
[0E6H]
INT0IF
INT0 pin
INT0 INTERRUPT
Edge selection
Register
2
2
Interrupt
goes
active
Interrupt
latched
Interrupt
processing
Interrupt
routine
8 f
XIN
max. 12 f
XIN
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