參數(shù)資料
型號: HMS38112
廠商: Electronic Theatre Controls, Inc.
英文描述: 4-BIT SINGLE CHIP MICROCOMPUTERS
中文描述: 4位單片機微機
文件頁數(shù): 37/73頁
文件大?。?/td> 505K
代理商: HMS38112
3-9
Watch Dog Timer (WDT)
Watch dog timer is organized binary of 14 steps. The signal of f
OSC
/48 cycle comes
in the first step of WDT after WDT reset. If this counter was overflowed, reset
signal automatically come out so that internal circuit is initialized.
The overflow time is 8
6
2
13
/f
OSC
(108.026ms at f
OSC
= 3.64MHz)
Normally, the binary counter must be reset before the overflow by using reset
instruction (WDTR), Power-on reset pulse or Low VDD detection pulse.
* It is constantly reset in STOP mode. When STOP is released, counting is
restarted. (Refer to STOP Operation>)
Fig 3-6 Block Diagram of Watch-dog Timer
Binary counter(14 steps)
RESET (edge-trigger)
f
OSC
/48
CPU reset
Reset
by instruction
Power-On Reset
Low VDD Detection
Chapter 3. Architecture
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