- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371861 > HMP9701EVAL2 (Intersil Corporation) AC’97 Audio Codec PDF資料下載
參數(shù)資料
| 型號： | HMP9701EVAL2 |
| 廠商： | Intersil Corporation |
| 元件分類： | Codec |
| 英文描述： | AC’97 Audio Codec |
| 中文描述： | AC\u0026#39;97音頻編解碼器 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 174K |
| 代理商： | HMP9701EVAL2 |
11
Pinout
HMP9701 (TQFP)
TOP VIEW
L
L
M
M
C
C
V
V
A
A
P
C
LINE_OUT_R
LINE_OUT_L
CAP2
CAP1
NC
AFILT3
AFILT2
AFILT1
V
REFOUT
V
REF
AGND
V
AA
M
V
A
C
C
N
N
N
N
N
N
N
A
V
DD
XTL_IN
XTL_OUT
GND
SDATA_OUT
BIT_CLK
GND
SDATA_IN
V
DD
SYNC
RESET
PC_BEEP
1
2
3
4
5
6
7
8
9
10
11
1213 14 15 16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Pin Descriptions
NAME
TQFP PIN
NUMBER
INPUT/
OUTPUT
DESCRIPTION
DIGITAL I/O
RESET
11
I
RESET - This active low signal causes a HMP9701 hardware reset that will return the control/status
registers to their default conditions.
SYNC
10
I
SYNC - 48kHz sync pulse which defines the beginning of serial audio I/O frames. Note: must be
synchronous to BIT_CLK.
BIT_CLK
6
O
BIT Clock - 12.288MHz serial data clock derived by dividing down 24.576MHz crystal input.
SDATA_OUT
5
I
Serial Data Out - Output bit stream that contains audio playback samples as well as control data.
This input is sampled on the falling edge of BIT_CLK.
SDATA_IN
8
O
Serial Data In - Input bit stream that contains recorded audio samples as well as codec status in-
formation. Data output on the rising edge of BIT_CLK.
ANALOG I/O
PC_BEEP
12
I
PC Beep. Mono Input for PC Beep pass through to LINE_OUT. This input is attenuated from 0dB
to 45dB in 3dB steps and then summed with left and right line outputs (LINE_OUT_L,
LINE_OUT_R)
PHONE
13
I
Phone. Mono Input from telephony subsystem speaker phone (or DLP - Down Line Phone)
MIC1
21
I
Microphone Input 1. The MIC input may be either line-level or -20dB from line-level. In the latter
case, a software controlled 20dB gain block may be activated.
MIC2
22
I
Microphone Input 2. The MIC input may be either line-level or -20dB from line-level. In the latter
case, a software controlled 20dB gain block may be activated.
LINE_IN_L
23
I
Left Line Input. The left line-level may be selected for recording via one of the stereo ADC’s via the
Input Mux. In addition, this input can be gained/attenuated from +12dB to -34.5dB in 1.5dB steps
and then summed with left line output (LINE_OUT_L).
HMP9701
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HMPVIDEVALISA | NTSC/PAL Video Decoder |
| HMP8115 | NTSC/PAL Video Decoder |
| HMP8115CN | NTSC/PAL Video Decoder |
| HMR100 | Hadware Manual |
| HMR-100 | Hadware Manual |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM-PCB | 制造商:PacTec 功能描述:CASE HAND-HELD PC BONE |
| HMPE | 制造商:MERITEK 制造商全稱:MERITEK ELECTRONICS CORPORATION 功能描述:Hi-Voltage Metallized Polyester Film Capacitors |
| HMPE101J3A | 制造商:MERITEK 制造商全稱:MERITEK ELECTRONICS CORPORATION 功能描述:Hi-Voltage Metallized Polyester Film Capacitors |
| HMPE682K3A | 制造商:MERITEK 制造商全稱:MERITEK ELECTRONICS CORPORATION 功能描述:Hi-Voltage Metallized Polyester Film Capacitors |
| HMPP-3860 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Low cost general purpose PIN diode |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。