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參數(shù)資料
| 型號： | HM628100LTTI-5SL |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | Wide Temperature Range Version 8 M SRAM (1024-kword x 8-bit) |
| 中文描述： | 寬溫版本八米的SRAM（1024 - KWord的× 8位） |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 91K |
| 代理商： | HM628100LTTI-5SL |
HM628100I Series
12
Low V
CC
Data Retention Characteristics
(Ta = –40 to +85
°
C)
Parameter
Symbol
Min
Typ
*
2
Max
Unit
Test conditions
*
1
V
CC
for data retention
V
DR
2.0
—
—
V
Vin
≥
0 V
(1) 0 V
≤
CS2
≤
0.2 V or
(2) CS2
≥
V
CC
– 0.2 V
CS1
≥
V
CC
– 0.2 V
V
= 3.0 V, Vin
≥
0 V
(1) 0 V
≤
CS2
≤
0.2 V or
(2) CS2
≥
V
CC
– 0.2 V,
CS1
≥
V
CC
– 0.2 V
See retention waveform
Data retention current
I
CCDR
—
0.8
10
μ
A
Chip deselect to data
retention time
t
CDR
0
—
—
ns
Operation recovery time
Notes: 1. CS2 controls address buffer,
WE
buffer,
CS1
buffer,
OE
buffer and Din buffer. If CS2 controls data
retention mode, Vin levels (address,
WE
,
OE
,
CS1
, I/O) can be in the high impedance state. If
CS1
controls data retention mode, CS2 must be CS2
≥
V
– 0.2 V or 0 V
≤
CS2
≤
0.2 V. The other
input levels (address,
WE
,
OE
, I/O) can be in the high impedance state.
2. Typical values are at V
CC
= 3.0 V, Ta = +25C and not guaranteed.
3. t
RC
= read cycle time.
t
R
t
RC
*
3
—
—
ns
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