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參數(shù)資料
| 型號(hào)： | HM62256BLTM-7UL |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Triple 3-Input Positive-AND Gates 14-CFP -55 to 125 |
| 中文描述： | 256k的SRAM（32 KWord的× 8位） |
| 文件頁數(shù)： | 19/20頁 |
| 文件大小： | 154K |
| 代理商： | HM62256BLTM-7UL |
HM62256B Series
19
Revision Record
Rev.
Date
Contents of Modification
Drawn by
Approved by
0.0
Sep. 10, 1993
Initial Issue
Y. Saito
K. Yoshizaki
1.0
Mar. 23, 1994
DC Characteristics
I
CC1
Typ: —/—/—/— mA to 33/29/26/24 mA
Deletion of HM62256BLT-7/10SL/12SL
Addition of HM62256BLTM-8/7SL/8SL(TFP-28DA)
AC Characteristics
Addition of note 12
Low V
data retention characteristics
V
max: — to 5.5 V
Note 2: 20
μ
A max at Ta = 0 to +40
°
C
to 10
μ
A max at Ta = 0 to +40
°
C
Deletion of description; (only for L-version)
Y. Saito
K. Yoshizaki
2.0
Oct. 31, 1994
Y. Saito
K. Yoshizaki
3.0
Jun. 19, 1995
Change of format
Deletion of HM62256BLP-8/10/12/8SL/10SL/12SL
Deletion of HM62256BLSP-8/10/12/8SL/10SL/12SL
Deletion of HM62256BLFP-8T/10T/12T
Deletion of HM62256BLFP-8SLT/10SLT/12SLT
Deletion of HM62256BLT-10/12/8SL
Deletion of HM62256BLTM-8SL
Addition of HM62256BLFP-4SLT/5SLT/7ULT
Addition of HM62256BLTM-4SLT/5SLT/7ULT
Features
Fast access time: 70/85/100/120 ns
to 45/55/70/85 ns
DC Characteristics
I
CC1
typ: 33/29/26/24 mA to —/—/33/29 mA
max: 60/50/50/45 mA to 70/60/60/50 mA
I
SB1
typ: 0.3/0.3
μ
A to 0.2/0.2/0.2
μ
A
max: 100/50
μ
A to 100/50/10
μ
A
Addition of note 3
AC Characteristics
Change order of notes.
Test Condition
Addition of HM62256B-4: 1TTL Gate + C
L
(100pF)
(Including scope & jig)
t
RC
min: 70/85/100/120 ns to 45/55/70/85 ns
t
AA
max: 70/85/100/120 ns to 45/55/70/85 ns
t
ACS
max: 70/85/100/120 ns to 45/55/70/85 ns
t
OE
max: 40/45/50/60 ns to 30/35/40/45 ns
t
CLZ
min: 10/10/10/10 ns to 5/5/10/10 ns
t
OHZ
max: 25/30/35/40 ns to 20/20/25/30 ns
t
OH
min: 5/5/10/10 ns 5/5/5/5 ns
t
WC
min: 70/85/100/120 ns to 45/55/70/85 ns
t
CW
min: 60/75/80/85 ns to 35/40/60/75 ns
t
AW
min: 60/75/80/85 ns to 35/40/60/75 ns
t
WP
min: 50/55/60/70 ns to 30/35/50/55 ns
t
WHZ
max: 25/30/35/40 ns to 20/20/25/30 ns
M. Higuchi
K. Yoshizaki
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM62256BLTM-8 | Dual J-K Negative-Edge-Triggered Flip-Flops With Preset And Clear 16-CDIP -55 to 125 |
| HM62256BLFP-5SLT | 256k SRAM (32-kword x 8-bit) |
| HM62256BLFP-7SLT | 256k SRAM (32-kword x 8-bit) |
| HM62256BLFP-7T | 256k SRAM (32-kword x 8-bit) |
| HM62256BLFP-7ULT | 256k SRAM (32-kword x 8-bit) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM62256BLTM-8 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:256k SRAM (32-kword x 8-bit) |
| HM62256BSERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IC-256K CMOS SRAM |
| HM62256FP10T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| HM62256FP-12T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| HM62256FP-15T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
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