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參數(shù)資料
| 型號(hào)： | HM621400H |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4M High Speed SRAM (4-Mword ×1-bit)(4M高速靜態(tài)RAM(4M字×1位)) |
| 中文描述： | 4分高速SRAM（4 Mword × 1位）（4分高速靜態(tài)隨機(jī)存儲(chǔ)器（4分字× 1位）） |
| 文件頁(yè)數(shù)： | 6/15頁(yè) |
| 文件大小： | 108K |
| 代理商： | HM621400H |
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HM621400H Series
6
AC Characteristics
(Ta = 0 to +70
°
C, V
CC
= 5.0 V
±
10 %, unless otherwise noted.)
Test Conditions
Input pulse levels: 3.0 V/0.0 V
Input rise and fall time: 3 ns
Input and output timing reference levels: 1.5 V
Output load: See figures (Including scope and jig)
Dout
255
480
5 V
5 pF
Output load (B)
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
WHZ
, and t
OW
)
Dout
RL=50
Output load (A)
1.5 V
Zo=50
Read Cycle
HM621400H
-10
-12
-15
Parameter
Symbol Min
Max
Min
Max
Min
Max
Unit
Notes
Read cycle time
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
t
OLZ
t
CHZ
t
OHZ
10
—
12
—
15
—
ns
Address access time
—
10
—
12
—
15
ns
Chip select access time
—
10
—
12
—
15
ns
Output enable to outpput valid
—
5
—
6
—
7
ns
Output hold from address change
3
—
3
—
3
—
ns
Chip select to output in low-Z
3
—
3
—
3
—
ns
1
Output enable to output in low-Z
0
—
0
—
0
—
ns
1
Chip deselect to output in high-Z
—
5
—
6
—
7
ns
1
Output disable to output in high-Z
—
5
—
6
—
7
ns
1
相關(guān)PDF資料 |
PDF描述 |
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| HM6216255HCLJP-10 | 4M High Speed SRAM (256-kword x 16-bit) |
| HM6216255HCLTT-10 | 4M High Speed SRAM (256-kword x 16-bit) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM621400HC | 制造商:HITACHI 制造商全稱(chēng):Hitachi Semiconductor 功能描述:4M High Speed SRAM (4-Mword x 1-bit) |
| HM621400HCJP-10 | 制造商:HITACHI 制造商全稱(chēng):Hitachi Semiconductor 功能描述:4M High Speed SRAM (4-Mword x 1-bit) |
| HM621400HCJP-12 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Instructions for Using SRAM Devices Technical Update/Device |
| HM621400HCLJP-10 | 制造商:HITACHI 制造商全稱(chēng):Hitachi Semiconductor 功能描述:4M High Speed SRAM (4-Mword x 1-bit) |
| HM621400HCLJP-12 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Instructions for Using SRAM Devices Technical Update/Device |
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