參數(shù)資料
型號: HM5225805B-B6
廠商: Elpida Memory, Inc.
英文描述: 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
中文描述: 256M LVTTL接口SDRAM的133 MHz/100 MHz的4 Mword】16位】4-bank/8-Mword】8位】4銀行/ 16 Mword】4位】4銀行PC/133,電腦/ 100內(nèi)存
文件頁數(shù): 22/63頁
文件大?。?/td> 462K
代理商: HM5225805B-B6
HM5225165B/HM5225805B/HM5225405B-75/A6/B6
Data Sheet E0082H10
22
Operation of the SDRAM
The following chapter shows operation example of the products below.
Organization
Input/output mask
CAS
latency
4-Mword
×
16-bit
×
4 bank
8-Mword
×
8-bit
×
4 bank
16-Mword
×
4-bit
×
4 bank
DQMU/DQML
2/3
DQM
DQM
Note:
and “AC Characteristics”).
The SDRAM should be used according to the product capability (See “Features”, “Pin Description”
Read/Write Operations
Bank active:
Before executing a read or write operation, the corresponding bank and the row address must be
activated by the bank active (ACTV) command. An interval of t
RCD
is required between the bank active
command input and the following read/write command input.
Read operation:
A read operation starts when a read command is input. Output buffer becomes Low-Z in
the (
CAS
Latency - 1) cycle after read command set. The SDRAM can perform a burst read operation.
The burst length can be set to 1, 2, 4, 8. The start address for a burst read is specified by the column address
and the bank select address (BA0/BA1) at the read command set cycle. In a read operation, data output starts
after the number of clocks specified by the
CAS
Latency. The
CAS
Latency can be set to 2 or 3.
When the burst length is 1, 2, 4, 8, the Dout buffer automatically becomes High-Z at the next clock after the
successive burst-length data has been output.
The
CAS
latency and burst length must be specified at the mode register.
相關(guān)PDF資料
PDF描述
HM5225805BLTT-75 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5225165B 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5225165B-75 Ultra-High-Precision SOT23 Series Voltage Reference
HM5225165B-A6 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5225165B-B6 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HM5225805BLTT-75 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5225805BLTT-A6 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5225805BLTT-B6 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5225805BTT-75 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
HM5225805BTT-A6 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM