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參數(shù)資料
| 型號： | HIP0045AB |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | Peripheral Driver |
| 英文描述： | 1.75 A 8 CHANNEL, LATCH BASED PRPHL DRVR, PDSO20 |
| 封裝： | PLASTIC, DSO-20 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大小： | 87K |
| 代理商： | HIP0045AB |
4
Open Load Threshold Voltage
VREF
Open Load Fault Condition, Fault Detected If
VOUT < VREF
0.32 x
VCC
-
0.4x
VCC
V
Open Load Pull-Down Current
ISK
No Load, VOUT = VBATT = 16V
20
-
100
A
Over-Current Shutdown Threshold, OUT0 - 5
ISC
VCC = 5V
1.05
1.4
2
A
Short Circuit Current Limit, OUT6, 7
ILIM
VCC = 5V
1.05
1.4
1.75
A
Short Circuit Shutdown Delay, OUT0 - 5
tSC
0.2
-
12
s
Disable Fault Detection Time, Channel IN0,
IN1 After Input Switch Transition
tDF
15
-
50
s
Over-Temperature Detection Threshold
TOFF
155
165
175
oC
LOGIC INPUTS (IN0, IN1, MOSI, SCK, RESET, CE)
Threshold Voltage at Falling Edge
VT-
0.2xVCC
--
V
Threshold Voltage at Rising Edge
VT+
-
0.7xVCC
V
Hysteresis Voltage
VH
VT+ - VT-
0.65
-
V
Input Current
IIN
VIN = VCC
-
+10
A
Input Pull-Up Resistance
RIN
50
80
200
k
Input Capacitance
CIN
-
10
pF
Input Frequency, IN0, IN15
fIN
DC
-
2
kHz
Active Supply Range for Reset State
Change at RESET Pin
VHCC_RS
T
RESET Pin Forced Reset. (Note: Normal VCC
Functional Operating Range is 4.0V to 5.5V)
3.1
-
5.5
V
Low VCC Active Reset Threshold
VLCC_RST Low VCC Forced Reset, (Low Voltage Reset
Active for 0 < VCC < VLCC_RST)
3.1
-
4
V
LOGIC OUTPUT (MISO)
Data Output LOW Voltage
VSOL
ISO = -3.2mA
-
0.2
0.4
V
Data Output HIGH Voltage
VSOH
ISO = -4mA
VCC -
0.4V
--
V
Output Three-State Leakage Current
ISOL
CE = High, 0V
≤ VSO ≤ VCC
-10
-
+10
A
Output Capacitance
CSO
fOPER = 3MHz
-
10
pF
Electrical Specications
VCC = 4.5V to 5.5V, TA = -40
oC to 125oC, Unless Otherwise Specied (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Serial Peripheral Interface Timing
(MOSI, MISO Load Capacitor = 100pF, See Figure 1)
PARAMETER
SYMBOL
TEST CONDITION
MIN
TYP
MAX
UNITS
Clock Frequency, 50% Duty Cycle
fCLK
3
-
MHz
Enable Lead Time
(SCK Change Low to High after CE = Low)
tLEAD
100
-
ns
Enable Lag Time
(Time for SCK Low before CE goes High)
tLAG
150
-
ns
Minimum Time SCK = High
tWSCKH
160
-
ns
Minimum Time SCK = Low
tWSCKL
160
-
ns
Data Setup Time (SCK Change from High to Low
after MOSI Data Valid)
tSU
20
-
ns
Data Hold Time (MOSI Data Hold Time SCK
Change from High to Low)
tH
-20
ns
Enable Time from CE = Low to Data at MISO
tEN
-
100
ns
Disable Time
(Time for CE Low to High to Output Data Float)
tDIS
-
100
ns
HIP0045
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