
7-1851
Pin Descriptions
40 LEAD
PDIP
44 LEAD
MQFP
PIN NAME
PIN DESCRIPTION
1
41
MODE
Mode input. Used to select between Synchronous Self Clocking (MODE = 1) or Synchronous Ex-
ternal Clocking (MODE = 0) for the Serial Port.
2
42
SCLK
Serial interface clock. Synchronizes serial data transfers. Data is input on the rising edge and out-
put on the falling edge.
3
43
SDO
Serial Data Out. Serial data is read from this line when using a 3-wire serial protocol such as the
Motorola Serial Peripheral Interface.
4
44
SDIO
Serial Data IN or OUT. This line is bidirectional programmable and interfaces directly to the Intel
Standard Serial Interface using a 2-wire serial protocol.
5
1
OSC
1
Oscillator clock input for the device. A crystal connected between OSC
1
and OSC
2
will provide a
clock to the device, or an external oscillator can drive OSC
1
. The oscillator frequency should be
3.6864MHz to maintain Line Noise Rejection.
6
2
OSC
2
DV
DD
DGND
Used to connect a crystal source between OSC
1
and OSC
2
. Leave open otherwise.
Positive Digital supply (+5V).
7
3, 30
8, 31
4, 29, 39
Digital supply ground.
9, 30
5, 6, 27, 28
AV
SS
V
INL1
V
INH1
V
INL2
V
INH2
V
INL3
V
INH3
V
INL4
V
INH4
V
INL5
V
INH5
V
INL6
V
INH6
V
INL7
V
INH7
V
INL8
V
INH8
V
CM
V
RLO
V
RHI
AV
DD
RST
Negative analog power supply (-5V).
10
7
Analog input low for Channel 1.
11
8
Analog input high for Channel 1.
12
9
Analog input low for Channel 2.
13
10
Analog input high for Channel 2.
14
11
Analog input low for Channel 3.
15
12
Analog input high for Channel 3.
16
13
Analog input low for Channel 4.
17
14
Analog input high for Channel 4.
18
15
Analog input low for Channel 5.
19
16
Analog input high for Channel 5.
20
17
Analog input low for Channel 6.
21
18
Analog input high for Channel 6.
22
19
Analog input low for Channel 7.
23
20
Analog input high for Channel 7.
24
21
Analog input low for Channel 8.
25
22
Analog input high for Channel 8.
26
23
Common mode voltage. Must be tied to the mid point of AV
DD
and AV
SS
.
External reference input. Should be negative referenced to V
RHI
.
External reference input. Should be positive referenced to V
RLO
.
Positive analog power supply (+5V).
27
24
28
25
29
26
32
31
Active low Reset pin. Used to initialize modulator, filter, RAMs, registers and state machines.
33
32
CA
Calibration active output. Indicates that at least one active channel is in a calibration mode.
34
33
MXC
Multiplexer control output. Indicates that the conversion for the active channel is complete.
35
34
A
0
A
1
A
2
EOS
Logical channel count output (LSB).
36
35
Logical channel count output.
37
36
Logical channel count output (MSB).
38
37
End of scan output. Signals the end of a channel scan (all active channels have been converted)
and data is available to be read. Remains low until data RAM is read.
39
38
RSTI/O
I/O reset (active low) input. Resets serial interface state machine only.
40
40
CS
Active low chip select pin. Used to select a serial data transfer cycle. When high the SDO and
SDIO pins are three-state.
HI7188