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參數(shù)資料
| 型號： | HI7188EVAL |
| 廠商： | Intersil Corporation |
| 英文描述： | 8-Channel, 16-Bit, High Precision, Sigma-Delta A/D Sub-System |
| 中文描述： | 8通道，16位，精度高，Σ-ΔA / D轉(zhuǎn)換子系統(tǒng) |
| 文件頁數(shù)： | 15/22頁 |
| 文件大小： | 156K |
| 代理商： | HI7188EVAL |
7-1861
Line Noise Rejection Off
Operation of the device is altered slightly when LNR is dis-
abled. Since the microsequencer is not synchronizing for
any line noise, the conversion rate increases to 260.3 con-
versions second/channel (10% increase). With LNR dis-
abled, a conversion scan involves converting only the
ACTIVE logical channels. When ACTIVELY converting on
less than 8 channels, this is the major speed advantage over
LNR enabled which sets conversion scan period based on
ALL eight logical channels. Refer to Table 3.
System Offset Calibration
The system offset calibration mode is a process that allows
the user to lump offset errors of external circuitry and the
internal errors of the HI7188 together and null them out. This
mode will convert the external differential signal applied to
the V
IN
inputs and then store that value in the offset calibra-
tion RAM for that physical channel. To invoke the system off-
set calibration the user applies the “zero scale” voltage to the
physical channel requiring calibration, then writes the related
CCR byte indicating offset calibration is required. The next
time this logical channel is converted, the microsequencer
performs calibration and updates the related offset RAM.
Next the internal microsequencer places that logical channel
back into the conversion mode and updates the CCR byte.
System Positive Full Scale Calibration
The system positive full scale calibration mode is a process
that allows the user to lump positive gain errors of external cir-
cuitry and the internal gain errors of the HI7188 together to
calculate the positive transfer function of the system. This
mode will convert the external differential signal applied to the
V
IN
inputs and then store that value in the system positive full
Scale calibration RAM for that physical channel. To invoke the
system positive full scale calibration the user applies the “pos-
itive full scale” voltage to the physical channel requiring cali-
bration, then writes the related CCR byte indicating positive
full scale calibration is required. The next time this logical
channel is converted, the microsequencer performs calibra-
tion and updates the related system positive full scale calibra-
tion RAM. Next the internal microsequencer places that
logical channel back into the conversion mode and updates
the CCR byte.
System Negative Full Scale Calibration
The system negative full scale calibration mode is a process
that allows the user to lump negative gain errors of external cir-
cuitry and the internal gain errors of the HI7188 together to cal-
culate the negative transfer function of the system. This mode
will convert the external differential signal applied to the VIN
inputs and then store that value in the system negative full
scale calibration RAM for that physical channel. To invoke the
system negative full scale calibration the user applies the “neg-
ative full scale voltage”, which must be equal to Vref, to the
physical channel requiring calibration, then writes the related
CCR byte indicating negative full scale calibration is
required(see note below). The next time this logical channel is
converted, the microsequencer performs calibration and
updates the related system negative full scale calibration RAM.
Next the internal microsequencer places that logical channel
back into the conversion mode and updates the CCR byte.
TEMPORARY NOTE: In bipolar mode, the user MUST
perform negative full scale calibration with the exact dif-
ferential voltage applied to the Vref pins, otherwise large
errors will occur at the zero crossing point. During nor-
mal conversions, the error occurs when the input is at
the offset calibration point. At this point, plus or minus
1/2 LSB, the output code will be either the true half scale
reading of 7FFF/8000 (offset binary coding) or negative
full scale 0000. This problem has been corrected with
the HI7188A.
Offset and Gain Adjust Limits
Whenever a calibration mode is used, there are limits to the
amount of offset and gain which can be adjusted. For both
bipolar and unipolar modes the minimum and maximum
input spans are 0.2 x V
REF
/GAIN and 1.2 x V
REF
/GAIN
respectively. In the unipolar mode the offset plus the span
cannot exceed the 1.2 x V
REF
/GAIN limit. So, if the span is
at its minimum value of 0.2 x V
REF
/GAIN, the offset must be
less than 1 x V
REF
/GAIN. In bipolar mode the span is equi-
distant around the voltage used for the zero scale point. For
this mode the offset plus half the span cannot exceed 1.2 x
V
REF
/GAIN. If the span is at
±
0.2 x V
REF
/GAIN
,
then the off-
set can not be greater than
±
2 x V
REF
/GAIN.
Range Detection
In addition to the calibration process, the converter detects over
range above positive full scale and under range below minus
full scale conditions. Over or under range detection affects the
output data coding as described in the Data Coding section.
Over range detection is identical for both bipolar and unipo-
lar operation. Over range is detected by comparing the offset
corrected filter output to the positive gain coefficient. If the
current offset corrected filter value is greater than the posi-
tive gain coefficient, an over range condition is detected.
In unipolar mode, under range is detected by sampling the
sign bit of the offset calibrated data. If the sign bit is logic 1,
signifying a negative voltage, an under range condition exists.
In bipolar mode, under range is detected by comparing the
offset corrected filter output to the negative gain coefficient.
If the current offset corrected filter value is less than the neg-
ative gain coefficient, an under range condition is detected.
Data Coding
The calibrated data can be obtained in one of various numerical
codes depending on the bipolar/unipolar mode bit and the two’s
complement coding bit. In bipolar mode, if the two’s comple-
ment bit is high, the output is two’s complement. In bipolar
mode, offset binary coding is used when the two’s complement
coding bit is low. In unipolar mode, only binary coding is avail-
able and the two’s complement coding bit is a don’t care.
The output coding for the HI7188 is shown in Tables 4 and 5.
V
ZS
represents the applied zero scale input during system
offset calibration. V
PFS
represents the applied positive full
scale input during system positive full scale calibration.
V
NFS
represents the applied negative full scale input during
system negative full scale calibration.
HI7188
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| HI7188IN | 8-Channel, 16-Bit, High Precision, Sigma-Delta A/D Sub-System |
| HI7188IP | 8-Channel, 16-Bit, High Precision, Sigma-Delta A/D Sub-System |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HI7188IN | 功能描述:CONV A/D 16BIT 8:1 MUX 44-MQFP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| HI7188IP | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 16BIT ADC 7188 DIP40 制造商:Harris Corporation 功能描述: |
| HI7190 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:null24-Bit, High Precision, Sigma Delta A/D Converter |
| HI7190 WAF | 制造商:Harris Corporation 功能描述: |
| HI7190_06 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:24-Bit, High Precision, Sigma Delta A/D Converter |
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