參數(shù)資料
型號(hào)： HI5960IA
廠商： INTERSIL CORP
元件分類： DAC
英文描述： CONNECTOR ACCESSORY
中文描述： PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 14-BIT DAC, PDSO28
封裝： PLASTIC, MO-153-AE, TSSOP-28
文件頁(yè)數(shù)： 4/12頁(yè)
文件大?。?/td> 88K
代理商： HI5960IA
4
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage DV
DD
to DCOM . . . . . . . . . . . . . . . . . . +5.5V
Analog Supply Voltage AV
DD
to ACOM. . . . . . . . . . . . . . . . . . +5.5V
Grounds, ACOM TO DCOM. . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (D9-D0, CLK, SLEEP). . . . . . . . DV
DD
+ 0.3V
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AV
DD
+ 0.3V
Analog Output Current (I
OUT
) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Thermal Resistance (Typical, Note 1)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range. . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(SOIC - Lead Tips Only)
θ
JA
(
o
C/W)
75
110
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AV
DD
= DV
DD
= +5V, V
REF
= Internal 1.2V, IOUTFS = 20mA, T
A
= 25
o
C for All Typical Values
PARAMETER
TEST CONDITIONS
T
A
= -40
o
C TO 85
o
C
UNITS
MIN
TYP
MAX
SYSTEM PERFORMANCE
Resolution
14
-
-
Bits
Integral Linearity Error, INL
“Best Fit” Straight Line (Note 8)
-5
±
2.5
+5
LSB
Differential Linearity Error, DNL
(Note 8)
-3
±
1.5
+3
LSB
Offset Error, I
OS
(Note 8)
-0.025
+0.025
% FSR
Offset Drift Coefficient
(Note 8)
-
0.1
-
ppm
FSR/
o
C
Full Scale Gain Error, FSE
With External Reference (Notes 2, 8)
-10
±
2
+10
% FSR
With Internal Reference (Notes 2, 8)
-10
±
1
+10
% FSR
Full Scale Gain Drift
With External Reference (Note 8)
-
±
50
-
ppm
FSR/
o
C
With Internal Reference (Note 8)
-
±
100
-
ppm
FSR/
o
C
Full Scale Output Current, I
FS
2
-
20
mA
Output Voltage Compliance Range
(Note 3, 8)
-0.3
-
1.25
V
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, f
CLK
(Note 3)
125
-
-
MHz
Output Settling Time, (t
SETT
)
±
0.05% (
±
8 LSB) (Note 8)
-
35
-
ns
Singlet Glitch Area (Peak Glitch)
R
L
= 25
(Note 8)
-
5
-
pVs
Output Rise Time
Full Scale Step
-
2.5
-
ns
Output Fall Time
Full Scale Step
-
2.5
-
ns
Output Capacitance
-
10
-
pF
Output Noise
IOUTFS = 20mA
-
50
-
pA/
√
Hz
IOUTFS = 2mA
-
30
-
pA/
√
Hz
AC CHARACTERISTICS
+5V Power Supply
Spurious Free Dynamic Range,
SFDR Within a Window
f
CLK
= 100MSPS, f
OUT
= 20.2MHz, 30MHz Span (Notes 4, 8)
-
77
-
dBc
f
CLK
= 100MSPS, f
OUT
= 5.04MHz, 8MHz Span (Notes 4, 8)
-
97
-
dBc
f
CLK
= 50MSPS, f
OUT
= 5.02MHz, 8MHz Span (Notes 4, 8)
-
97
-
dBc
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