參數(shù)資料
| 型號： | HI5860IBZ-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | CONV D/A 12BIT 130MSPS 28-SOIC |
| 標準包裝： | 1 |
| 設置時間： | 35ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 200mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 28-SOIC W |
| 包裝： | 剪切帶 (CT) |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 130M |
| 其它名稱： | HI5860IBZ-TCT |
3
FN4654.7
February 6, 2008
Pin Descriptions
PIN NUMBER
PIN NAME
PIN DESCRIPTION
1 through 12
D11 (MSB) Through
D0 (LSB)
Digital Data Bit 11, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit).
13,14
NC
No Connect. (Available as 2 additional LSBs on the HI5960, 14-bit device).
15
SLEEP
Control Pin for Power-Down Mode. Sleep Mode is active high; connect to ground for Normal Mode. Sleep
pin has internal 20
μA active pull-down current.
16
REFLO
Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable internal
reference.
17
REFIO
Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is
enabled. Use 0.1F cap to ground when internal reference is enabled.
18
FSADJ
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output
Current = 32 x VFSADJ/RSET.
19
COMP1
For use in reducing bandwidth/noise. Recommended: Connect 0.1F to AVDD.
21
IOUTB
The complementary current output of the device. Full scale output current is achieved when all input bits
are set to binary 0.
22
IOUTA
Current output of the device. Full scale output current is achieved when all input bits are set to binary 1.
23
COMP2
Connect 0.1F capacitor to ACOM.
24
AVDD
Analog Supply (+2.7V to +5.5V).
20, 25
ACOM
Connect to Analog Ground.
26
DCOM
Connect to Digital Ground.
27
DVDD
Digital Supply (+2.7V to +5.5V).
28
CLK
Clock Input. Input data to the DAC passes through the “master” latches when the clock is low and is
latched into the “master” latches when the clock is high. Data presented to the “slave” latch passes
through when the clock is logic high and is latched into the “slave” latches when the clock is logic low.
Adequate setup time must be allowed for the MSBs to pass through the thermometer decoder before the
clock goes high. This master-slave arrangement comprises an edge-triggered flip-flop, with the DAC
being updated on the rising clock edge. For optimum spectral performance, it is recommended that the
clock edge be skewed such that set-up time is larger than the hold time.
HI5860
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相關代理商/技術參數(shù) |
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|---|---|
| HI5860S0ICEVALI | 制造商:Harris Corporation 功能描述: |
| HI5860SOICEVAL1 | 功能描述:數(shù)據(jù)轉換 IC 開發(fā)工具 HI5860 EVAL PL ATFORM PKG RoHS:否 制造商:Texas Instruments 產品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| HI5865 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:12-Bit, 65 MSPS A/D Converter |
| HI5865EVAL1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:12-Bit, 65 MSPS A/D Converter |
| HI5865IN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:12-Bit, 65 MSPS A/D Converter |
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