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參數(shù)資料
| 型號(hào)： | HI5805BIB |
| 廠商： | INTERSIL CORP |
| 元件分類： | ADC |
| 英文描述： | 12-Bit, 5MSPS A/D Converter |
| 中文描述： | 1-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大?。?/td> | 113K |
| 代理商： | HI5805BIB |
126
Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to
evaluate the dynamic performance of the HI5805. A low
distortion sine wave is applied to the input, it is coherently
sampled, and the output is stored in RAM. The data is then
transformed into the frequency domain with an FFT and
analyzed to evaluate the dynamic performance of the A/D.
The sine wave input to the part is -0.5dB down from full scale
for all these tests. SNR and SINAD are quoted in dB. The
distortion numbers are quoted in dBc (decibels with respect
to carrier) and
DO NOT
include any correction factors for
normalizing to full scale.
Signal-to-Noise Ratio (SNR)
SNR is the measured RMS signal to RMS noise at a
specified input and sampling frequency. The noise is the
RMS sum of all of the spectral components except the
fundamental and the first five harmonics.
Signal-to-Noise + Distortion Ratio (SINAD)
SINAD is the measured RMS signal to RMS sum of all
other spectral components below the Nyquist frequency,
f
S
/2, excluding DC.
Effective Number Of Bits (ENOB)
The effective number of bits (ENOB) is calculated from the
SINAD data by:
where: V
CORR
= 0.5dB.
V
CORR
adjusts the ENOB for the amount the input is below
fullscale.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first 5 harmonic
components to the RMS value of the fundamental input
signal.
2nd and 3rd Harmonic Distortion
This is the ratio of the RMS value of the applicable
harmonic component to the RMS value of the fundamental
input signal.
Spurious Free Dynamic Range (SFDR)
SFDR is the ratio of the fundamental RMS amplitude to the
RMS amplitude of the next largest spur or spectral
component in the spectrum below f
S
/2.
Intermodulation Distortion (IMD)
Nonlinearities in the signal path will tend to generate
intermodulation products when two tones, f
1
and f
2
, are
present at the inputs. The ratio of the measured signal to
the distortion terms is calculated. The terms included in the
calculation are (f
1
+ f
2
), (f
1
- f
2
), (2f
1
), (2f
2
), (2f
1
+ f
2
),
(2f
1
- f
2
), (f
1
+ 2f
2
), (f
1
- 2f
2
). The ADC is tested with each
tone 6dB below full scale.
Transient Response
Transient response is measured by providing a full-scale
transition to the analog input of the ADC and measuring the
number of cycles it takes for the output code to settle within
12-bit accuracy.
Over-Voltage Recovery
Over-voltage Recovery is measured by providing a full-scale
transition to the analog input of the ADC which overdrives
the input by 200mV, and measuring the number of cycles it
takes for the output code to settle within 12-bit accuracy.
Full Power Input Bandwidth (FPBW)
Full power input bandwidth is the analog input frequency at
which the amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sinewave.
The input sinewave has an amplitude which swings from -f
S
to +f
S
. The bandwidth given is measured at the specified
sampling frequency.
Timing Definitions
Refer to Figure 1, Internal Circuit Timing, and Figure 2,
Input-To-Output Timing, for these definitions.
Aperture Delay (t
AP
)
Aperture delay is the time delay between the external
sample command (the falling edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Jitter (t
AJ
)
Aperture Jitter is the RMS variation in the aperture delay due
to variation of internal clock path delays.
Data Hold Time (t
H
)
Data hold time is the time to where the previous data (N - 1)
is no longer valid.
Data Output Delay Time (t
OD
)
Data output delay time is the time to where the new data (N)
is valid.
Data Latency (t
LAT
)
After the analog sample is taken, the digital data is output on
the bus at the third cycle of the clock. This is due to the
pipeline nature of the converter where the data has to ripple
through the stages. This delay is specified as the data
latency. After the data latency time, the data representing
each succeeding sample is output at the following clock
pulse. The digital data lags the analog input sample by 3
clock cycles.
ENOB = SINAD + V
CORR
-1.76
)
/6.02,
HI5805
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| HI5805 | 12-Bit, 5MSPS A/D Converter |
| HI5805EVAL1 | 12-Bit, 5MSPS A/D Converter |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI5805BIBZ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 28 INDTEMP A/D 12BIT 5MSPS 0 5LSB V-REF RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| HI5805EVAL1 | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開(kāi)發(fā)工具 HI5805 EVAL PL ATFORM RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| HI5806IB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HI5808 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:12-Bit, 9MSPS A/D Converter |
| HI5808_01 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:12-Bit, 9MSPS A/D Converter |
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