Data Output Delay, tOD - 11.7 - ns Data Latency, tLAT
參數(shù)資料
型號(hào): HI5662/6IN
廠商: Intersil
文件頁(yè)數(shù): 12/14頁(yè)
文件大小: 0K
描述: ADC DUAL 8-BIT 60MSPS 44-MQFP
標(biāo)準(zhǔn)包裝: 96
位數(shù): 8
采樣率(每秒): 60M
數(shù)據(jù)接口: 并聯(lián)
功率耗散(最大): 670mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-QFP
供應(yīng)商設(shè)備封裝: 44-MQFP(10x10)
包裝: 管件
輸入數(shù)目和類型: 4 個(gè)單端,單極;2 個(gè)差分,雙極
3-7
Data Output Delay, tOD
-
11.7
-
ns
Data Latency, tLAT
For a Valid Sample (Note 2)
6
Cycles
Power-Up Initialization
Data Invalid Time (Note 2)
-
20
Cycles
Sample Clock Pulse Width (Low)
(Note 2)
7.5
8.3
-
ns
Sample Clock Pulse Width (High)
(Note 2)
7.5
8.3
-
ns
Sample Clock Duty Cycle Variation
±5%
POWER SUPPLY CHARACTERISTICS
Analog Supply Voltage, AVCC
(Note 2)
4.75
5.0
5.25
V
Digital Supply Voltage, DVCC1 and DVCC2
(Note 2)
4.75
5.0
5.25
V
Digital Output Supply Voltage, DVCC3
At 3.0V (Note 2)
2.7
3.0
3.3
V
At 5.0V (Note 2)
4.75
5.0
5.25
V
Supply Current, ICC
fS = 60MSPS
-
130
-
mA
Power Dissipation
-
650
670
mW
Offset Error Sensitivity,
VOS
AVCC or DVCC = 5V ±5%
-
±0.125
-
LSB
Gain Error Sensitivity,
FSE
AVCC or DVCC = 5V ±5%
-
±0.15
-
LSB
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock low and DC input.
Electrical Specications
AVCC1,2 = DVCC1,2 = +5.0V, DVCC3 = +3.0V; VRIN = 2.50V; fS = 60MSPS at 50% Duty Cycle;
CL = 10pF; TA = 25
oC; Differential Analog Input; Unless Otherwise Specied (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HI5662
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