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參數(shù)資料
| 型號： | HI5634CB |
| 廠商： | INTERSIL CORP |
| 元件分類： | XO, clock |
| 英文描述： | High Performance Programmable Phase-Locked Loop for LCD Applications |
| 中文描述： | 250 MHz, VIDEO CLOCK GENERATOR, PDSO24 |
| 封裝： | PLASTIC, MS-013AD, SOIC-24 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 131K |
| 代理商： | HI5634CB |
9
Detailed Register Description
Register: 0h
Name: Input Control
Access: Read/Write
BIT NAME
BIT #
RESET VALUE
DESCRIPTION
PDEN
0
1
Phase/Frequency Detector Enable - 0 = External Enable (Phase/Frequency Detector controlled by PDEN
(pin 5) only), 1 = Always Enabled (default).
PD_POL
1
0
Phase/Frequency Detector Enable Polarity - Used only when (Reg0 [0]=0).
0 = Not inverted (default, PDEN input (pin 5) is active high),1 = Inverted (PDEN input (pin 5) is active low).
REF_POL
2
0
Phase/Frequency Detector External Reference Polarity - Edge of input signal on which Phase Detector
triggers. 0 = Rising Edge (default), 1 = Falling Edge.
FBK_POL
3
0
External Feedback Polarity - Edge of EXTFB (pin 6) signal on which Phase/Frequency Detector triggers
when external feedback is used (Reg0 [4]=1). 0 = Positive Edge (default), 1 = Negative Edge.
FBK_SEL
4
0
External Feedback Select - 0 = Internal Feedback (default), 1 = External Feedback.
FUNC_SEL
5
0
Function Output Select - Selects re-clocked output to FUNC (pin 15).
0 = Recovered HSYNC (default, regenerated HSYNC output), 1 = External HSYNC (Schmitt-trigger
conditioned input from HSYNC (pin 7)).
EN_PLS
6
1
OutputsPLLLockStatus(Reg12[1])
on LOCK/REF pin.
EN_PLS
EN_DLS
IN_SEL
LOCK/REF (14)
0
0
N/A
0
EN_DLS
7
0
Outputs DPA Lock Status
(Reg12[0]) on LOCK/REF pin.
Bits 6, 7 enable multiple functions at
LOCK/REF output (pin 14), as
shown in table at right.
0
1
N/A
1 if DPA Locked, 0 Otherwise
1
0
N/A
1 if PLL Locked, 0 Otherwise
1
1
0
Post Schmitt Trigger HSYNC(7)
XOR REF_POL
1
1
1
F
OSC
÷
OSC_DIV
Register: 1h
Name: Loop Control Register
Access: Read/Write
(Note 8)
BIT NAME
BIT #
RESET VALUE
DESCRIPTION
PFD0-2
0-2
0
Phase/Frequency Detector Gain.
BIT 2
BIT 1
BIT 0
PFD GAIN (
μ
A/2
π
RAD)
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
Reserved
3
0
Reserved
PSD0-1
4-5
0
Post-Scaler Divider - Divides the output of the
VCO prior to the DPA and Feedback Divider.
BIT 5
BIT 4
PSD DIVIDER
0
0
2 (Default)
0
1
4
1
0
8
1
1
16
Reserved
6-7
0
Reserved
HI5634
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