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參數(shù)資料
| 型號(hào)： | HI5634CB |
| 廠商： | INTERSIL CORP |
| 元件分類： | XO, clock |
| 英文描述： | High Performance Programmable Phase-Locked Loop for LCD Applications |
| 中文描述： | 250 MHz, VIDEO CLOCK GENERATOR, PDSO24 |
| 封裝： | PLASTIC, MS-013AD, SOIC-24 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 131K |
| 代理商： | HI5634CB |
12
I
2
C Data Format
(Notes 11-14)
I
2
C Data Characteristics
NOTE: These waveforms are from “The I
2
C bus and how to use it,” published by Philips Semiconductor. The document can be obtained from:
http://www-us2.semiconductors.philips.com/acrobat/various/i2c_bus_specification_1995.pdf.
RANDOM REGISTER WRITE PROCEDURE
S 0 1 0 0 1 1 X W
P
7 Bit Address
Register Address
Data
A
A
A
RANDOM REGISTER READ PROCEDURE
S 0 1 0 0 1 1 X W
S 0 1 0 0 1 1 X R
A P
7 Bit Address
Register Address
7 Bit Address
Data
A
A
A
SEQUENTIAL REGISTER WRITE PROCEDURE
S 0 1 0 0 1 1 X W
P
7 Bit Address
Register Address
Data
Data
A
A
A
A
A
SEQUENTIAL REGISTER READ PROCEDURE
S 0 1 0 0 1 1 X W
S 0 1 0 0 1 1 X R
A
A P
7 Bit Address
Register Address
7 Bit Address
Data
Data
A
A
A
Direction:
= Bus Host to Device
= Device to Bus Host
NOTES:
11. All values are transmitted with the most significant bit first and the least significant bit last.
12. The value of the X-bit equals the logic state of pin 13 (I
2
CADR).
13. R = Read Command = 1, W = Write Command = 0.
14. S = Start Condition, A = Acknowledge, A = No Acknowledge, P = Stop Condition. See “I
2
C Data Characteristics” for description.
SDA
SCL
DATA LINE STABLE:
DATA VALID
CHANGE
OF DATA
ALLOWED
BIT TRANSFER ON THE I
2
C BUS
START AND STOP CONDITIONS
ACKNOWLEDGE ON THE I
2
C BUS
SDA
SCL
S
START
CONDITION
P
STOP
CONDITION
S
START
CONDITION
1
2
7
8
9
DATA OUTPUT BY
TRANSMITTER
DATA OUTPUT BY
RECEIVER
SCL FROM MASTER
CLOCK PULSE FOR
ACKNOWLEDGMENT
HI5634
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