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參數(shù)資料
| 型號： | HI3318JIP |
| 廠商： | INTERSIL CORP |
| 元件分類： | ADC |
| 英文描述： | 8-Bit, 15 MSPS, Flash A/D Converter |
| 中文描述： | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 109K |
| 代理商： | HI3318JIP |
4-1459
stage amplifier at its intrinsic trip point removes any tracking
differences between the first and second amplifier stages. The
cascaded auto-balance (CAB) technique, used here,
increases comparator sensitivity and temperature tracking.
In the “Sample Unknown” phase, all ladder tap switches and
comparator shorting switches are opened. At the same time
V
lN
is switched to the first set of commutating capacitors. Since
the other end of the capacitors are now looking into an effec-
tively open circuit, any input voltage that differs from the previ-
ous tap voltage will appear as a voltage shift at the comparator
amplifiers. All comparators that had tap voltages greater than
V
lN
will go to a “high” state at their outputs. All comparators that
had tap voltages lower than V
lN
will go to a “l(fā)ow” state.
The status of all these comparator amplifiers is AC coupled
through the second-stage comparator and stored at the end
of this phase (
φ
2) by a latching amplifier stage. The latch
feeds a second latching stage, triggered at the end of
φ
1.
This delay allows comparators extra settling time. The status
of the comparators is decoded by a 256 to 9-bit decoder
array, and the results are clocked into a storage register at
the end of the next
φ
2.
A 3-stage buffer is used at the output of the 9 storage
registers which are controlled by two chip-enable signals.
CE1 will independently disable B1 through B6 when it is in a
high state. CE2 will independently disable B1 through B8
and the OF buffers when it is in the low state.
To facilitate usage of this device, a phase control input is
provided which can effectively complement the clock as it
enters the chip.
Continuous-Clock Operation
One complete conversion cycle can be traced through the
HI3318 via the following steps. (Refer to timing diagram.) With
the phase control in a “l(fā)ow” state, the rising edge of the clock
input will start a “sample” phase. During this entire “high” state
of the clock, the comparators will track the input voltage and the
first-stage latches will track the comparator outputs. At the fall-
ing edge of the clock, all 256 comparator outputs are captured
by the 256 latches. This ends the “sample” phase and starts the
“auto-balance” phase for the comparators. During this “l(fā)ow”
state of the clock, the output of the latches settles and is cap-
tured by a second row of latches when the clock returns high.
The second-stage latch output propagates through the decode
array, and a 9-bit code appears at the D inputs of the output
registers. On the next falling edge of the clock, this 9-bit code is
shifted into the output registers and appears with time delay t
D
as valid data at the output of the three-state drivers. This also
marks the end of the next “sample” phase, thereby repeating
the conversion process for this next cycle.
Pulse-Mode Operation
The HI3318 needs two of the same polarity clock edges to
complete a conversion cycle: If, for instance, a negative
going clock edge ends sample “N”, then data “N” will appear
after the next negative going edge. Because of this require-
ment, and because there is a maximum sample time of
500ns (due to capacitor droop), most pulse or intermittent
sample applications will require double clock pulsing.
If an indefinite standby state is desired, standby should be in
auto-balance, and the operation would be as in Figure 3A.
If the standby state is known to last less than 500ns and low-
est average power is desired, then operation could be as in
Figure 3B.
Increased Accuracy
In most cases the accuracy of the HI3318 should be suffi-
cient without any adjustments. In applications where accu-
racy is of utmost importance, five adjustments can be made
to obtain better accuracy, i.e., offset trim; gain trim; and
1
/
4
,
1
/
2
and
3
/
4
point trim.
Offset Trim
In general, offset correction can be done in the preamp cir-
cuitry by introducing a dc shift to V
lN
or by the offset trim of
the op amp. When this is not possible the V
REF
- input can
be adjusted to produce an offset trim. The theoretical input
voltage to produce the first transition is
1
/
2
LSB. The equa-
tion is as follows:
V
lN
(0 to 1 transition) =
1
/
2
LSB =
1
/
2
(V
REF
/256)
= V
REF
/512.
If V
lN
for the first transition is less than the theoretical, then a
single-turn 50
pot connected between V
1
- and ground
will accomplish the adjustment. Set V
lN
to
/
2
LSB and trim
the pot until the 0-to-1 transition occurs.
If V
lN
for the first transition is greater than the theoretical,
then the 50
pot should be connected between V
REF
- and a
negative voltage of about 2 LSBs. The trim procedure is as
stated previously.
Gain Trim
In general, the gain trim can also be done in the preamp
circuitry by introducing a gain adjustment for the op amp.
When this is not possible, then a gain adjustment circuit
should be made to adjust the reference voltage. To perform
this trim, V
lN
should be set to the 255 to overflow transition.
That voltage is
1
/
3
LSB less than V
REF
+ and is calculated as
follows:
V
lN
(255 to 256 transition) = V
REF
- V
REF
/512
= V
REF
(511/512).
To perform the gain trim, first do the offset trim and then
apply the required V
lN
for the 255 to overflow transition. Now
adjust V
REF
+ until that transition occurs on the outputs.
+10V TO 30V
INPUT
3
2
1
8
4
7
6
+
10
μ
F, TAN
18
(NOTE 1)
5K
IOT
V
REF
+
(PIN 22)
4.7
μ
F,
TAN/IOV
CW
(NOTE 1)
1.5K
CA3085E
+
NOTE:
cap. Parts noted should have low temperature drift.
FIGURE 11. TYPICAL VOLTAGE REFERENCE SOURCE FOR
DRIVING V
REF
+ INPUT
Bypass V
REF
+ to analog GND near A/D with 0.1
μ
F ceramic
HI3318
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