參數(shù)資料
型號： HI3318JIP
廠商： INTERSIL CORP
元件分類： ADC
英文描述： 8-Bit, 15 MSPS, Flash A/D Converter
中文描述： 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDIP24
封裝： PLASTIC, DIP-24
文件頁數(shù)： 3/12頁
文件大小： 109K
代理商： HI3318JIP
4-1454
Absolute Maximum Ratings
T
A
= 25
o
C
Thermal Information
DC Supply Voltage Range (V
DD
or V
AA
+) . . . . . . . . . . -0.5V to +8V
(Referenced to V
SS
or V
AA
- Terminal, Whichever is
More Negative)
Input Voltage Range
CE2 and CE1 . . . . . . . . . . . . . . . . . . . . V
AA
- -0.5V to V
DD
+ 0.5V
Clock, Phase, V
REF
-,
1
/
2
Ref. . . . . . . V
AA
- -0.5V to V
AA
+ + 0.5V
Clock, Phase, V
REF
-,
1
/
4
Ref. . . . . . . . V
SS
- -0.5V to V
DD
+ 0.5V
V
IN
,
3
/
4
REF, V
REF
+. . . . . . . . . . . . . . .V
AA
- -0.5V to V
AA
- + 7.5V
Output Voltage Range, . . . . . . . . . . . . . . . V
SS
- 0.5V to V
DD
+ 0.5V
Bits 1-8, Overflow (Outputs Off)
DC Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
20mA
Clock, Phase, CE1, CE2, V
IN
, Bits 1-8, Overflow
Recommended V
AA
+ Operating Range. . . . . . . . . . . . . . . V
DD
±
1V
Recommended V
AA
- Operating Range . . . . . . . . . . . . . . . V
SS
±
1V
Operating Conditions
Operating Voltage Range (V
DD
or V
AA
+). . . 4V (Min) to 7.5V (Max)
Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Thermal Resistance (Typical, Note 1)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
θ
JA
(
o
C/W)
60
75
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
At 25
o
C, V
AA
+ = V
DD
= 5V, V
REF
+ = 6.4V, V
REF
- = V
AA
- = V
SS
, CLK = 15MHz,
All Reference Points Adjusted, Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM PERFORMANCE
Resolution
8
-
-
Bits
Integral Linearity Error
-
-
±
1.5
+1, -0.8
LSB
Differential Linearity Error
-
-
LSB
Offset Error, Unadjusted
V
IN
= V
REF
- +
1
/
2
LSB
V
IN
= V
REF
+ -
1
/
2
LSB
-0.5
4.5
6.4
LSB
Gain Error, Unadjusted
-1.5
0
1.5
LSB
DYNAMIC CHARACTERISTICS
Maximum Input Bandwidth
(Note 1) HI3318
2.5
5.0
-
MHz
Maximum Conversion Speed
CLK = Square Wave
15
17
-
MSPS
Signal to Noise Ratio, SNR
f
S
= 15MHz, f
IN
= 100kHz
f
S
= 15MHz, f
IN
= 4MHz
-
47
-
dB
-
43
-
dB
Signal to Noise Ratio, SINAD
f
S
= 15MHz, f
IN
= 100kHz
f
S
= 15MHz, f
IN
= 4MHz
-
45
-
dB
-
35
-
dB
Total Harmonic Distortion, THD
f
S
= 15MHz, f
IN
= 100kHz
f
S
= 15MHz, f
IN
= 4MHz
f
S
= 15MHz, f
IN
= 100kHz
f
S
= 15MHz, f
IN
= 4MHz
Unadjusted
-
-46
-
dBc
-
-36
-
dBc
Effective Number of Bits, ENOB
-
7.2
-
Bits
-
5.5
-
Bits
Differential Gain Error
-
2
-
%
Differential Phase Error
Unadjusted
-
1
-
%
ANALOG INPUTS
Full Scale Range, V
IN
and (V
REF
+) - (V
REF
-)
Input Capacitance, V
IN
Input Current, V
IN
, (See Text)
REFERENCE INPUTS
Notes 2, 4
4
-
7
V
-
30
-
pF
V
IN
= 5.0V, V
REF
+ = 5.0V
-
-
3.5
mA
Ladder Impedance
270
500
800
=RMS Noise
=
---------------------------------------------------------------
HI3318
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