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參數(shù)資料
| 型號(hào)： | HI3318 |
| 廠商： | Intersil Corporation |
| 英文描述： | RELAY SSR SPST 120MA 4-DIP |
| 中文描述： | 8位，15 MSPS的，閃光的A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 109K |
| 代理商： | HI3318 |
4-1458
Theory of Operation
A sequential parallel technique is used by the HI3318 con-
verter to obtain its high speed operation. The sequence con-
sists of the “Auto-Balance” phase,
φ
1, and the “Sample
Unknown” phase,
φ
2. (Refer to the circuit diagram.) Each con-
version takes one clock cycle (see Note). With the phase con-
trol (pin 19) high, the “Auto-Balance” (
φ
1) occurs during the
high period of the clock cycle, and the “Sample Unknown” (
φ
2)
occurs during the low period of the clock cycle.
NOTE: The device requires only a single phase clock The terminol-
ogy of
φ
1 and
φ
2 refers to the high and low periods of the same clock.
During the “Auto-Balance” phase, a transmission switch is
used to connect each of the first set of 256 commutating
capacitors to their associated ladder reference tap. Those
tap voltages will be as follows:
V
TAP
(N) = [(N/256) V
REF
] - (1/512) V
REF
]
= [(2N - 1)/512] V
REF
,
Where:
V
TAP
(n) = reference ladder tap voltage at point n,
V
REF
= voltage across V
REF
- to V
REF
+,
N = tap number (1 through 256).
The other side of these capacitors are connected to single-
stage amplifiers whose outputs are shorted to their inputs by
switches. This balances the amplifiers at their intrinsic trip
points, which is approximately (V
AA
+ - V
AA
-)/2. The first set
of capacitors now charges to their associated tap voltages.
At the same time a second set of commutating capacitors and
amplifiers is also auto-balanced. The balancing of the second-
FIGURE 10. ENOB vs INPUT FREQUENCY
(Continued)
f
I
(MHz)
8.0
5.0
E
7.6
7.2
6.8
6.4
6.0
5.6
5.2
4.4
4.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
f
S
= 15MHz
Pin Descriptions
PIN
NAME
DESCRIPTION
1
B1
Bit 1 (LSB)
Output Data Bits
(High = True)
2
B2
Bit 2
3
B3
Bit 3
4
B4
Bit 4
5
B5
Bit 5
6
B6
Bit 6
7
B7
Bit 7
8
B8
Bit 8 (MSB)
9
OF
1
/
4
R
V
SS
V
DD
CE2
Overflow
Reference Ladder
1
/
4
Point
Digital Ground
10
11
12
Digital Power Supply, +5V
13
Three-State Output Enable Input,
Active Low, See Truth Table.
14
CE1
Three-State Output Enable Input
Active High. See Truth Table.
15
V
REF
-
V
IN
V
AA
-
CLK
Reference Voltage Negative Input
16
Analog Signal Input
17
Analog Ground
18
Clock Input
19
PHASE
Sample clock phase control input.
When PHASE is low, “Sample Un-
known” occurs when the clock is low
and “Auto Balance” occurs when the
clock is high (see text).
20
1
/
2
R
V
IN
V
REF
+
3
/
4
R
V
AA
+
Reference Ladder Midpoint
21
Analog Signal Input
22
Reference Voltage Positive Input
Reference Ladder
3
/
4
Point
Analog Power Supply, +5V
23
24
CHIP ENABLE TRUTH TABLE
CE1
CE2
B1 - B8
OF
0
1
Valid
Valid
1
1
Three-State
Valid
X
0
Three-State
Three-State
X = Don’t Care
HI3318
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