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參數(shù)資料
| 型號： | HI3318 |
| 廠商： | Intersil Corporation |
| 英文描述： | RELAY SSR SPST 120MA 4-DIP |
| 中文描述： | 8位，15 MSPS的，閃光的A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 109K |
| 代理商： | HI3318 |
4-1455
DIGITAL INPUTS
Low Level Input Voltage, V
OL
CE1, CE2
Note 4
-
-
0.2V
DD
0.2V
AA
V
Phase, CLK
Note 4
-
-
V
High Level Input Voltage, V
IN
CE1, CE2
Note 4
0.7V
DD
0.7V
AA
-
-
-
V
Phase, CLK
Note 4
-
-
V
μ
A
pF
Input Leakage Current, I
I
(Except CLK Input)
Input Capacitance, C
I
DIGITAL OUTPUTS
Note 3
±
0.2
3
±
5
-
-
Output Low (Sink) Current
V
O
= 0.4V
V
O
= 4.5V
4
10
-
mA
Output High (Source) Current
-4
-6
-
mA
μ
A
pF
Three-State Output Off-State Leakage Current, I
OZ
Output Capacitance, C
O
TIMING CHARACTERISTICS
Auto Balance Time,
φ
1
-
±
0.2
4
±
5
-
-
33
-
∞
500
ns
Sample Time,
φ
2
Aperture Delay
Note 4
25
-
ns
-
15
-
ns
Aperture Jitter
-
100
-
ps
Data Valid Time, t
D
Data Hold Time, t
H
Output Enable Time, t
EN
Output Disable Time, t
DIS
POWER SUPPLY CHARACTERISTICS
Note 4
-
50
65
ns
Note 4
25
40
-
ns
-
18
-
ns
-
18
-
ns
Device Current (I
DD
+ I
A
) (Excludes I
REF
)
Continuous Conversion (Note 4)
Auto Balance (
φ
1)
-
30
60
mA
-
30
60
mA
NOTES:
1. A full scale sine wave input of greater than f
CLK
/2 or the specified input bandwidth (whichever is less) may cause an erroneous code. The
-3dB bandwidth for frequency response purposes is greater than 30MHz.
2. V
IN
(Full Scale) or V
REF
+ should not exceed V
AA
+ + 1.5V for accuracy.
3. The clock input is a CMOS inverter with a 50k
feedback resistor and may be AC coupled with 1V
P-P
minimum source.
4. Parameter not tested, but guaranteed by design or characterization.
Timing Waveforms
FIGURE 1. INPUT TO OUTPUT TIMING DIAGRAM
Electrical Specifications
At 25
o
C, V
AA
+ = V
DD
= 5V, V
REF
+ = 6.4V, V
REF
- = V
AA
- = V
, CLK = 15MHz,
All Reference Points Adjusted, Unless Otherwise Specified
(Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
COMPARATOR DATA IS LATCHED
DECODED DATA IS SHIFTED
TO OUTPUT REGISTERS
φ
2
SAMPLE
N
φ
2
φ
1
φ
1
φ
2
CLOCK (PIN 18)
IF PHASE (PIN 19)
IS LOW
CLOCK IF
PHASE IS HIGH
AUTO
BALANCE
SAMPLE
N + 1
t
D
t
H
DATA
N - 2
AUTO
BALANCE
SAMPLE
N + 2
DATA
N - 1
DATA
N
HI3318
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