參數(shù)資料
型號(hào): HI2303JCQ
廠商: HARRIS SEMICONDUCTOR
元件分類: ADC
英文描述: Triple 8-Bit, 50 MSPS, Video A/D Converter with Clamp Function
中文描述: 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP80
文件頁(yè)數(shù): 7/18頁(yè)
文件大?。?/td> 162K
代理商: HI2303JCQ
7
Digital Output Voltage
V
OH
X
OE
= 0V
DV
DD
= 5V
I
OH
= -2mA
DV
DD
-0.8
-
-
V
V
OL
I
OL
= 4mA
-
-
0.4
V
V
OH
X
OE
= 0V
DV
DD
= 3.3V
I
OH
= -1.2mA
DV
DD
-0.8
-
-
V
V
OL
I
OL
= -2.4mA
-
-
0.4
V
NOTES:
2. The offset voltage E
OB
is a potential difference between A
RB
, B
RB
, C
RB
and a point of position where the voltage drops equivalent to
1
/
2
LSB
of the voltage when the output data changes from “00000000” to “00000001”. E
OR
is a potential difference between A
RT
, B
RT
, C
RT
and a po-
tential of point where the voltage rises equivalent to
1
/
2
LSB of the voltage when the output data changes from “11111111” to “11111110”.
(2V + E
-E
) of each channel
OT
OB
3.
.
Timing
f
C
= 50 MSPS, AV
DD
= 5V, DV
DD
= 5V or 3.3V, V
RB
= 0.5V, V
RT
= 2.5V, T
A
= 25
o
C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output Data Delay
t
PLH
C
L
= 15pF
XOE = 0V
DV
DD
= 5V
4.5
8.5
11
ns
t
PHL
4.5
7.4
11
ns
t
PLH
DV
DD
= 3.3V
3.8
10
13.8
ns
t
PHL
3.8
6.7
13.8
ns
Three-State Output Enable Time
t
PZH
R
L
= 1k
CL = 15
P
F
XOE = 0V
3V
DV
DD
= 5V
4.2
7.1
11.3
ns
t
PZL
4.2
8.0
11.3
ns
t
PZH
DV
DD
= 3.3V
3.5
8.4
12.8
ns
t
PZL
3.5
7.2
12.8
ns
Three-State Output Disable Time
t
PHZ
R
L
= 1k
C
L
= 15pF
XOE = 0V
3V
DV
DD
= 5V
3.6
6.8
9.5
ns
t
PLZ
3.6
6.3
9.5
ns
t
PHZ
DV
DD
= 3.3V
2.9
6.8
10.5
ns
t
PLZ
2.9
6.0
10.5
ns
Sampling Delay
t
SD
-
-3
-
ns
Set-up Time
t
S
3.5
-
-
ns
Hold Time
t
H
4.5
-
-
ns
Pulse Width
CLP
2.0
-
-
Cycles
Pulse Width
SY
1
-
-
Cycles
Electrical Specifications
f
C
= 50 MSPS, AV
DD
= 5V, DV
DD
= 3.0V to 5.0V, V
RB
= 0.5V, V
RT
= 2.5V, T
A
= 25
o
C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Full scale input ratio =
--------------------------------------------------------------------------------------------------------------------------
-1 x100(%)
HI2303
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