參數(shù)資料
型號(hào): HI2303JCQ
廠商: HARRIS SEMICONDUCTOR
元件分類(lèi): ADC
英文描述: Triple 8-Bit, 50 MSPS, Video A/D Converter with Clamp Function
中文描述: 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP80
文件頁(yè)數(shù): 4/18頁(yè)
文件大?。?/td> 162K
代理商: HI2303JCQ
4
30,35,41,42,62,
68
AV
DD
Analog +5V Power Supply.
43
59
TEST
I
Normally open. Pull-down
resistors are incorporated.
44
45
46
XAOE
XBOE
XCOE
I
Output Enable Input. When these
pins are Low, data is output from
the digital output pins. When these
pins are High, the digital output
pins are High impedance. The A, B
and C Channels can be controlled
separately. Also, these pins are not
synchronized with the clock signal.
Pull-down
resistors
incorporated.
are
47
48
49
CTL0
CTL1
CLT2
I
Determines
mode. See the Mode tables and
Timing
Charts.
resistors are incorporated.
the
digital
output
Pull-down
50
SY
I
Controls the digital output mode
switching timing. The mode is
switched
by
transition point where this pin
changes from Low to High. See
the Mode Tables and Timing
Charts for details. A pull-down
resister is incorporated.
detecting
the
51
SEL
I
Controls the CLP signal polarity.
When this pin is Low, CLP is High
active.
When this pin is High, CLP is Low
active. This pin has a built-in pull-
down resistor.
52
CLK
I
Clock Input. A pull-down resistor is
incorporated.
53
CLP
I
Clamp Pulse Input. The polarity
can be set to either High or Low by
setting SEL. This pin has a built-in
pull-down resistor.
54
55
56
57
REF0
REF1
REF2
REF3
I
Determines
reference data. See the mode
tables for the set data. These pins
are not synchronized with the
clock
input
signal.
resistors are incorporated.
the
clamp
circuit
Pull-down
58
CLE
I
ClampEnable.WhenthispinisLow
the clamp circuit does not operate.
When this pin is High, the clamp
circuit
operates.
resistor is incorporated.
A
pull-down
Pin Description
(Continued)
PIN NO.
SYMBOL
EQUIVALENT CIRCUIT
DESCRIPTION
AV
DD
AV
SS
AV
DD
AV
SS
HI2303
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