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參數(shù)資料
| 型號： | HI1106JCP |
| 廠商： | INTERSIL CORP |
| 元件分類： | DAC |
| 英文描述： | RELAY SPDT 16A 24VDC PC MT |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁數(shù)： | 14/14頁 |
| 文件大?。?/td> | 691K |
| 代理商： | HI1106JCP |
10-14
Notes On Application
1. Setting of V
REF
Pin (Pin 24)
The full-scale voltage of the D/A output is determined by
V
SET
input voltage. As about (1.2V - V
EE
) DC voltage is
generated at V
REF
pin (Pin 1) by connecting an external
resistor from V
REF
pin to V
EE
pin (Pin 23), divide this volt-
age using resistors and apply it to V
SET
pin as Figure 22.
Example of usage:
The full-scale voltage of the D/A output can be determined
from the following equation:
V
FS
= 1.2 (V
SET
- V
EE
) (R
L
> 10k
, 0.4V
≤
V
SET
≤
1.2V
Select an external resistor R (connected to V
REF
pin) so
that I
REF
(current of an external resistor) is within the value
indicated as the Recommended Operating Conditions of
(-3mA < I
REF
< -0.4mA).
2. Phase Relation Between Data and Clock
To make the best use of the inherent characteristics of
this D/A converter the phase relation between the data
and clock applied from the exterior, should be properly
set. Set up time (t
S
) and Hold time (t
H
) should be as indi-
cated in the Electrical Specifications. For t
S
and t
H
refer
to Figure 6 in the Timing Waveform. Also, set the clock
pulse width according to the Recommended Operating
Conditions.
3. D/A Output Pin Load
Receive the D/A output stage at high impedance, so as to
obtain:
R
L
> 10k
,
C
L
< 20pF.
4. Noise Reduction
Refer to the following notes in order to minimize noise
contamination that occurs from outside the IC and
penatrates D/A output.
The power supply line and ground line should be made
as wide as possible when fixed to the printed circuit
board. Analog and Digital circuits should be separated.
Connected a bypass capacitor between each of DV
CC
(Pin 6) and DGND1 (Pin 7); AGND1, 2 (Pins 2, 3) and
V
EE
(Pin 23); V
SET
(Pin 24) and V
EE
(Pin 23),
respectively.
FIGURE 21. DUAL POWER SUPPLY
Application Circuits
12
11
10
9
8
7
6
5
4
3
2
1
13
14
15
16
17
18
19
20
21
22
23
24
D5
D4
D3
D2
D1
D0 (LSB)
NC
NC
V
EE
V
SET
8-BIT
DIGITAL
INPUT
(TTL)
3K
D6
D7
(MSB)
CLK
CLK (TTL)
DGND1
V
CC
DGND2
AOUT
AGND2
AGND1
V
REF
R
D/A
OUT
LPF
MATCHING RESISTANCE FOR LPF
DV
CC
AV
CC
DGND AGND
V
EE
+
-
FIGURE 22.
V
REF
V
SET
V
EE
R
23
24
1
I
REF
V
SET
SINGLE POWER SUPPLY
DUAL POWER SUPPLY
V
EE
AGND
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