
COMMUNICATING WITH THE CONTROL AND
STATUS REGISTERS
LABELRECOGNITIONOPTION
LOADING LABELS
READING LABELS
Pin 27, C/ , must be high to read the status register or write
the control register.
Reading the status register resets
errors. Thereisnoprovisiontoreadthecontrolregister.
Pin5mustbehighiflabelrecognitionisselectedineitherthe
8 or 32 bit modes and all eight label buffers must be written
usingredundantlabels,ifnecessary.
Thechipcomparestheincominglabeltothestoredlabels. If
a match is found, the data is processed. If a match is not
found,noindicatorsofreceivingARINCdataarepresented.
AfterthewritethatchangesCR7from0to1,thenext8writes
of data (C/
is a zero for data) will load the label registers.
Labels must be loaded whenever pin 5 goes from low to
high.
After the write that changes CR1 from 0 to 1, the next 8 data
readsarelabels.
D
D
PIN 6 - MR
When MR is a 1, the control word is set to 0X10 0101 (CR7 -
CR0).
For the receiver this sets up 8 bit mode with the
receiver and parity enabled. MR also initializes the registers
and logic. The first ARINC reception will only occur
wordgap.
IN8 - RXRDY
In 8 bit mode, this pin goes high whenever 8 bits are received
withouterror. In32bitmode,thispingoeshighafterall32bits
are received with no error. This flag may be inhibited for one
ARINC word if CR3 is programmed to 1. This flag is also
inhibitedinlabelrecognitioniftheincomingARINClabeldoes
notmatchoneofthestored8labels.
PIN12 - RXC
This pin must have a clock applied that is 4X the desired
receivefrequency.
PIN13 - FCR
In 8 bit mode, this pin flags the first character (byte) received.
In 32 bit mode, this pin goes high for a valid 32 bit word. The
pinisnotaffectedbyCR3programming.
a
after
P
USING THE RECEIVER (cont.)
receiver is not programmable to the 32 bit "extended buffer"
mode nor to the label recognition mode.
receiver:
Affecting the
PIN14 - RXD0andPIN16 - RXD1
These pins must be 5 volt logic levels.
translator between the ARINC bus and these inputs.
Typically a receiver chip, such as the HI-8482orHI-8588
is inserted between the ARINC bus and the logic chips.
RXD0 is looking for a high level for zero inputs and RXD1 is
looking for a high level for one inputs. When both inputs are
lowthisisreferredtoastheNullstate.
There must be a
By writing to the Control Register and reading the Status
Register the controlling processor can operate the receiver
without hardware interrupts.
combination with the wiring of pin 5 was explained above.
The Status Register bits pertaining to the receiver are
explainedbelow:
The Control Register in
SOFTWARE CONTROL OF THE RECEIVER
* CR3 will be automatically reset to 0 after being programmed
to a 1 at the completion of an ARINC word reception. This
allowsasoftwarelabelrecognitiondifferentfromtheautomatic
optionavailable.
CONTROL PROGRAM PIN 5
BIT NAME
VALUE
VALUE
OPERATION
CR1
X
0
1
0
1
1
No action
No action
Next 8 data read cycles will read
stored labels. One time only sequence
on each transiton of CR1 to a 1.
CR2
0
1
X
X
Receiver is disabled
Receiver is enabled
CR3*
0
1
X
X
RXRDY goes high normally
Blocks RXRDY for one ARINC word
CR4
0
1
X
X
Self test disabled
Self test enabled
CR5
0
0
No parity errors enabled and 32nd
bit is data
Parity error flag enabled
32 bit "extended mode" enabled and
parity enabled.
8 bit "one byte at a time" mode and
parity enabled.
1
0
0
1
1
1
CR7
X
0
1
0
1
1
Label recognition not programmable
Label recognition disabled
Label recognition enabled
SR1
0
1
No receiver data
Receiver data ready
SR3
0
1
No parity error
Parity error - Parity was even
SR4
0
1
Receiver data not overwritten
Receiver data was overwritten
SR5
0
1
Receiver data received without framing error
Framing error - Did not receive exactly 32
good bits
SR6
0
1
Did not receive first byte
Received first byte - Same flag as pin 13
STATUS BIT VALUE
MEANING
HI-6010
HOLT INTEGRATED CIRCUITS
3