參數(shù)資料
型號: HI-6010JF
廠商: HOLT INTEGRATED CIRCUITS INC
元件分類: 微控制器/微處理器
英文描述: ARINC 429 TRANSMITTER/RECEIVER FOR 8 BIT BUS
中文描述: 1 CHANNEL(S), SERIAL COMM CONTROLLER, PQCC28
封裝: ROHS COMPLIANT, PLASTIC, LCC-28
文件頁數(shù): 2/12頁
文件大小: 101K
代理商: HI-6010JF
PIN
SYMBOL
FUNCTION
DESCRIPTION
1
V
POWER
0.0 Volts
2
WEF
OUTPUT
Error indication if high. Status register must be read to determine specific error.
3
INPUT
Enables data transmission when low.
4
TXC
INPUT
Source clock for data transmission. 4 times bit rate.
5
HFS
INPUT
Hardware feature select.
6
MR
INPUT
Master reset, active high.
7
TXE
OUTPUT
Low when transmission in progress.
8
RXRDY
OUTPUT
High when data of received word is available.
9
TXRDY
OUTPUT
High when data of a transmitted word may be input.
10
TXD0
OUTPUT
"Zeroes" data output of transmitter.
11
TXD1
OUTPUT
"Ones" data output of transmitter.
12
RXC
INPUT
Source clock for data reception. 4 times bit rate.
13
FCR
OUTPUT
First character received flag.
14
RXD0
INPUT
"Zeroes" data input to receiver.
15
V
POWER
5 Volts ±5%
16
RXD1
INPUT
"Ones" data input to receiver.
17
D0
I / O
Data bus
18
D1
I / O
Data bus
19
D2
I / O
Data bus
20
D3
I / O
Data bus
21
D4
I / O
Data bus
22
D5
I / O
Data bus
23
D6
I / O
Data bus
24
D7
I / O
Data bus
25
INPUT
8 bit data bus input control active low.
26
INPUT
Chip select, active low.
27
C/
INPUT
High for control or status register operations, low for data
28
INPUT
8 bit data bus output control, active low.
SS
DD
CTS
WE
CS
D
RE
PIN DESCRIPTIONS
HI-6010
USING THE RECEIVER
The receiver logic is independent of the transmitter except in
thefollowingways:
1.
SelfTest
2.
ParityOption
In self test, the transmitter outputs route to the receiver inputs
internally ignoring the external inputs. Also in self test, the
externalreceiverclockisreplacedwiththetransmitterclock.
The parity option affects both the receiver and transmitter.
Eitherbothareoperationalorneither.
WEF is an error indicator.
"underwrite" (failure to keep up with byte loading) and pin 2
It goes high for a transmitter
HARDWARE CONTROL OF THE RECEIVER
PIN 2 - WEF
goes high for any one of three receiver errors. The status
registerwillshowwhichofthethreeerrorsoccurred:
SR3
SR4
SR5
Received a parity error
Data Overwritten
Receiving sequence error
The possible Receiver sequence errors are:
1. RXD0 and RXD1 simultaneously a one.
2. Less than 32 bits before 3 nulls.
3. More than 32 bits.
There are no errors flagged for labels received that don't
match stored labels when in the label recognition mode.
ErrorsareclearedbyMRorbyreadingtheStatusRegister.
This pin, along with the control register, sets up the
functioning (e.g. modes) of the chip.
If HFS is low, the
Status Register Bit
Error
PIN5-HFS andtheCONTROLREGISTER
HOLT INTEGRATED CIRCUITS
2
相關(guān)PDF資料
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HI-6010JTF ARINC 429 TRANSMITTER/RECEIVER FOR 8 BIT BUS
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