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參數(shù)資料
| 型號： | HFCT-5402D |
| 英文描述： | 2488 Mb/s Single Mode Fiber Transceiver for SONET OC-48/SDH STM-16 and ATM(應用于SONET OC-48/SDH STM-16 和ATM的2488 Mb/s 單模式光收發(fā)器) |
| 中文描述： | 2488 Mb / s的掃描隧道顯微鏡的SONET OC-48/SDH單模光纖收發(fā)器- 16和ATM（應用于的SONET OC-48/SDH的STM - 16和自動柜員機的2488 Mb / s的單模式光收發(fā)器） |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 1017K |
| 代理商： | HFCT-5402D |
2
CDR Function
In normal operation, the CDR data
loop is able to acquire and
maintain bit lock with the use of
the external reference clock. The
recovered clock is used to re-time
the quantizer data output, which
completes the full CDR function.
The relative timing relationship
between the output retimed data
and the recovered clock signals is
shown graphically in Figure 2.
The voltage swing measurement
method is also shown for clock
and data outputs.
For input optical power greater
than the specified receiver
sensitivity of -18.5 dBm, the
bit-error-ratio will be better than
1 x 10
-10
. The SD (signal detect)
will be deasserted when loss of
optical signal occurs.
Reference Clock
With ‘intermittent’ or ‘no data
condition’ the output clock will
slowly drift away from the
2.48832 GHz. The reference clock
Figure 1. Block Diagram
enables the VCXO to acquire and
maintain lock. Ref Clk input is self
biasing and 50 input terminated.
Temperature Range
The HFCT-5402D is specified for
operation over normal commercial
temperature range of 0° to +70°C
with recommended metal shield
Figure 2a. Relative Timing Relationship Between Output
Retimed Data and Recovered Clock Signals
in place (see Figure 3) and with
2 m/s forced airflow around the
transceiver. In the event a 2 m/s
airflow is not available due to
chassis restrictions, high
temperature operation will be
limited to +60°C.
ELECTRICAL SUBASSEMBLY
100 nF
DATA
CLOCK
CLOCK
REF CLK
SIGNAL DETECT
CLOCK & DATA
RECOVERY
AND POST
AMPLIFIER IC
LASER
DRIVER
IC
PRE-
AMPLIFIER
IC
LASER
PIN PHOTODIODE
DUPLEX SC
RECEPTACLE
TOP VIEW
DATA
LASER BIAS MONITOR +
LASER BIAS MONITOR -
TRANSMIT
DISABLE
DATA
+V
CCT
DATA
+V
CCR
1 nF
100
W
V
EE
Figure 2b. Logic Voltage Values
BAUD INTERVAL
CLOCK PERIOD
RD
RD
CLK
CLK
80 ps
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
Data In/Out V p-p - Single Ended
Differential
Clock Out V p-p
Differential
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參數(shù)描述 |
|---|---|
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