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參數(shù)資料
| 型號： | HFCT-5402D |
| 英文描述： | 2488 Mb/s Single Mode Fiber Transceiver for SONET OC-48/SDH STM-16 and ATM(應(yīng)用于SONET OC-48/SDH STM-16 和ATM的2488 Mb/s 單模式光收發(fā)器) |
| 中文描述： | 2488 Mb / s的掃描隧道顯微鏡的SONET OC-48/SDH單模光纖收發(fā)器- 16和ATM（應(yīng)用于的SONET OC-48/SDH的STM - 16和自動柜員機(jī)的2488 Mb / s的單模式光收發(fā)器） |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 1017K |
| 代理商： | HFCT-5402D |
18
Figure 24. Typical Transmitter Data Eye Diagram with OC-48 Mask
Table 1. HFCT-5402 Transceiver Module Pin Out Table
Pin
Mounting Studs
Symbol
Functional Description
The mounting studs are provided for transceiver mechanical attachment to the circuit
board. They are embedded in the nonconductive plastic housing and are not connected
to the transceiver internal circuit. They should be soldered into plated-through holes on
the printed circuit board.
Reference Clock
An externally generated clock of 19.44 MHz (For 2.48832 Gb/s) or 1/128 of Bit Rate
with a 100 ppm tolerance must be provided for operation of the Clock recovery circuit.
This single-ended input requires external ac coupling and clock input of 250 mV p-p
minimum and 6 ns maximum rise time. The input stage is internally biased and 50
W
terminated.
Signal Ground
Directly connect this pin to the signal ground plane.
Received Recovered Clock Out Bar - Internally ac coupled (1 nF).
1
Ref Clk
2
V
EE
3
Clk-
The falling edge occurs in the middle of the Received Data baud period.
Terminate this differential clock output with 50 ohms line to the follow-on device.
If this output is not used terminate with 50 ohms to V
EE
.
Received Recovered Clock Out - Internally ac coupled (1 nF)
4
Clk+
The rising edge occurs in the middle of the Received Data baud period.
Terminate this differential clock output with 50 ohms line to the follow-on device.
If this output is not used terminate with 50 ohms to V
EE
.
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