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參數(shù)資料
| 型號： | HFBR-5103T |
| 英文描述： | 1300 nm 2000 m，F(xiàn)DDI, 100 Mbps ATM, and Fast Ethernet Transceivers in Low Cost 1x9 Package Style(1300 nm 2000 m，F(xiàn)DDI, 100 Mbps ATM, 快速以太網(wǎng)收發(fā)器（低價格 1x9 封裝類型）) |
| 中文描述： | 1300納米2000米，光纖分布式數(shù)據(jù)介面，100 Mbps的自動取款機(jī)，并在低成本1x9封裝形式快速以太網(wǎng)收發(fā)器（1300納米2000米，光纖分布式數(shù)據(jù)介面，100 Mbps的自動取款機(jī)，快速以太網(wǎng)收發(fā)器（低價格1x9封裝類型）） |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 351K |
| 代理商： | HFBR-5103T |
7
The jitter specifications stated in
the following 1300 nm
transceiver specification tables
are derived from the values in
Tables E1 of Annexes E. They
represent the worst case jitter
contribution that the transceivers
are allowed to make to the overall
system jitter without violating the
Annex E allocation example. In
practice the typical contribution
of the Agilent transceivers is well
below these maximum allowed
amounts.
Recommended Handling
Precautions
Agilent recommends that normal
static precautions be taken in the
handling and assembly of these
transceivers to prevent damage
which may be induced by
electrostatic discharge (ESD).
The HFBR-5100 series of
transceivers meet MIL-STD-883C
Method 3015.4 Class 2 products.
Care should be used to avoid
shorting the receiver data or
signal detect outputs directly to
ground without proper current
limiting impedance.
Solder and Wash Process
Compatibility
The transceivers are delivered
with protective process plugs
inserted into the duplex SC or
duplex ST connector receptacle.
This process plug protects the
optical subassemblies during
wave solder and aqueous wash
processing and acts as a dust
cover during shipping.
These transceivers are compat-
ible with either industry standard
wave or hand solder processes.
Shipping Container
The transceiver is packaged in a
shipping container designed to
protect it from mechanical and
ESD damage during shipment or
storage.
Board Layout - Decoupling
Circuit and Ground Planes
It is important to take care in the
layout of your circuit board to
achieve optimum performance
from these transceivers. Figure 7
provides a good example of a
schematic for a power supply
decoupling circuit that works well
with these parts. It is further
recommended that a contiguous
ground plane be provided in the
circuit board directly under the
transceiver to provide a low
inductance ground for signal
return current. This recommenda-
tion is in keeping with good high
frequency board layout practices.
Figure 7. Recommended Decoupling and Termination Circuits
NO INTERNAL CONNECTION
NO INTERNAL CONNECTION
HFBR-510X
TOP VIEW
V
EE
1
RD
2
RD
3
SD
4
V
CC
5
V
CC
6
TD
7
TD
8
V
EE
9
C1
C2
L1
L2
R2
R3
R1
R4
C5
C3
C4
R9
R10
V
FILTER
AT V
PINS
TRANSCEIVER
R5
R7
R6
R8
C6
RD
RD
SD
V
CC
TD
TD
TERMINATION
AT PHY
DEVICE
INPUTS
NOTES:
THE SPLIT-LOAD TERMINATIONS FOR ECL SIGNALS NEED TO BE LOCATED AT THE INPUT
OF DEVICES RECEIVING THOSE ECL SIGNALS. RECOMMEND 4-LAYER PRINTED CIRCUIT
BOARD WITH 50 OHM MICROSTRIP SIGNAL PATHS BE USED.
R2 = R3 = R5 = R7 = R9 = 82 OHMS.
C1 = C2 = C3 = C5 = C6 = 0.1 μF.
C4 = 10 μF.
L1 = L2 = 1 μH COIL OR FERRITE INDUCTOR.
TERMINATION
AT TRANSCEIVER
INPUTS
Rx
Rx
Tx
Tx
V
CC
V
CC
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HFBR-5103TE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
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| HFBR-5103TP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| HFBR-5104 | 制造商:HP 制造商全稱:Agilent(Hewlett-Packard) 功能描述:FDDI, 100 Mbps ATM, and Fast Ethernet Transceivers in Low Cost 1x9 Package Style |
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