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參數(shù)資料
| 型號： | HFA5253CB |
| 廠商： | Harris Corporation |
| 英文描述： | 800MHz, Ultra High-Speed Monolithic Pin Driver |
| 中文描述： | 800MHz的，超高速單片管腳驅(qū)動 |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 527K |
| 代理商： | HFA5253CB |
93
Functional Block Diagram
The HFA5253 functional block diagram is shown in on the first
page of this data sheet.
The control inputs, DATA and DATA, determine the output level.
If DATA is at logic “1” and DATA is at logic “0”, the output level
will be the same as V
HIGH
. If DATA is at logic “0” and DATA is at
logic “1”, the output will be the same as V
LOW
. The control
inputs, HIZ and HIZ, cause the output to become either active
or high-impedance. If HIZ is at logic “1” and HIZ is at logic “0”,
the output will be in high impedance mode. If HIZ is at logic “0”
and HIZ is at logic “1”, the output will be enabled. The output
impedance in the enabled mode is trimmed to 50
.
Circuit Schematic
The Pin Driver circuit consists of a switch, an output buffer,
and two differential control elements as shown in the circuit
Schematic Diagram.
A two stage approach, separating the switch from the output
buffer, allows the speed and accuracy requirements of the
switch to be de-coupled from the load driving capability of
the buffer.
The patented switch circuitry [3] uses cascaded emitter
followers as input buffers and also to switch the input V
HIGH
and V
LOW
to node VSO. Dual differential pairs controlled by the
data timing (DATA and DATA) direct current to select either the
V
HIGH
or V
LOW
switch. Matching transistor types and
transdiodes improve linearity and lowers the voltage offset and
offset drift. Stacking two emitter-base junctions allows the
V
HIGH
to V
LOW
range to be extended to two Emitter - Base
breakdown voltages of the process. The speed of the pin driver
is largely determined by the current flowing through the switch
stage and the collector-base capacitance of the output stage
transistors connected to the node VSO. The Slew Rate Control
Pins, +SRC and -SRC, allow the user to control the amount of
current available in the V
HIGH
and V
LOW
switch, respectively
and thus the slew rate of node VSO.
The output stage consists of cascaded emitter followers
constructed in a typical push-pull manner as shown in the
Schematic Diagram. However, transdiodes are added to
increase the voltage breakdown characteristics of the output
during high impedance mode. HIZ and HIZ control the mode
of the output stage. A trimmed, NiCr resistor is added to
provide the 50
output impedance.
Overall, a symmetry of device types and paths is constructed
to improve slew and delay symmetry. Both the V
HIGH
to V
OUT
path and the V
LOW
to V
OUT
path contain three NPN and
three PNP transistors operating at similar collector currents.
Thus the transient response of V
HIGH
to V
LOW
and V
LOW
to
V
HIGH
are kept symmetrical. Also, a trimmable current
reference (not shown) allows the AC parameters to be
adjusted to maintain unit to unit consistency.
Application Information
The HFA5253 is a pin driver designed for use in automatic
test equipment (ATE) and high speed pulse generators. Pin
drivers, especially those with very high-speed performance,
have generally been implemented with discrete transistors
(sometimes GaAs) on a circuit board or in a hybrid. Recent
IC process improvements, specifically Harris’ UHF1 process
[2], have enabled the manufacturing of the 500MHz and
800MHz silicon monolithic pin drivers, HFA5250, HFA5251
and now the HFA5253.
Schematic Diagram
V
CC1
V
EE1
DATA
DATA
V
HIGH
V
LOW
VSO
V
OUT
HIZ
HIZ
V
CC2
V
EE2
HIZ CONTROL
OUTPUT STAGE
SWITCHING STAGE
V
HIGH
/V
LOW
CONTROL
+SRC
-SRC
HFA5253
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|---|---|
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