參數(shù)資料
型號： HFA3860A
廠商： Intersil Corporation
英文描述： Direct Sequence Spread Spectrum Baseband
中文描述： 直接序列擴頻基帶
文件頁數(shù)： 27/39頁
文件大?。?/td> 251K
代理商： HFA3860A
2-157
Bit 3
This control bit selects the active level of the Carrier Sense (CRS) output pin which is an output pin at the test port, pin 45.
Logic 1 = CRS Active 0
Logic 0 = CRS Active 1
Bit 2
This control bit selects the active level of the transmit enable (TX_PE) input pin 2.
Logic 1 = TX_PE Active 0
Logic 0 = TX_PE Active 1
Bit 1
This control bit selects the phase of the transmit output clock (TXCLK) pin 4.
Logic 1 = Inverted TXCLK
Logic 0 = NON-Inverted TXCLK
Bit 0
Must be set to “0”
CONFIGURATION REGISTER 1 ADDRESS (04h) I/O POLARITY
CONFIGURATION REGISTER 2 ADDRESS (08h) TX AND RX CONTROL
Write to control, Read to verify control, setup while TX_PE and RX_PE are low
Bit 7
MCLK control.
0 = 44MHz
1 = 22MHz
All signal modes supported.
1MBPS and 2MBPS, B/QPSK 11 Chip sequence mode only. Reduced power mode.
Bit 6
TX Rotation
0 = Normal
1 = Invert Q Out
Bit 5
RX Rotation
0 = Normal
1 = Invert Q IN
Bit 4
A/D Calibration
0 = A/D_CAL Off
1 = A/D_CAL On
Bit 3
A/D Calibration control (only valid if A/D Calibration is on).
0 = A/D Calibration only while in receive tracking mode (A/D Calibration set on signals only).
1 = A/D Calibration while receive RX_PE is active (in this mode, the A/D Calibration will be set primarily on noise).
Bit 2
This bit enables/disables energy detect (ED) for the CCA function.
0 = ED Off
1 = ED On
Bit 1
MD_RDY Start. Sets where MD_RDY will become active.
0 = After SFD detect (normal). This allows the header fields to be enveloped by MD_RDY.
1 = After Header CRC verify and start of MPDU. Header data can be read from Configuration Registers.
Bit 0
TX and RX Clock
0 = Enable Gated clocks (normal). RX clock will come on to clock out header fields, go off during CRC and come back on
for MPDU data. Header rate is 1MHz, data rate is variable. TXCLK comes on after TXRDY active.
1 = Clocks start as soon as modem starts tracking and remain on until either header checks fail or until RX_ PE goes back
low. This is only usable in the 1MBPS and 2MBPS modes. TXCLK comes on after TX_PE active.
CONFIGURATION REGISTER 3 ADDRESS (0Ch) A/D CAL POS
Bits 0 - 7
This 8-bit control register contains a binary value used for positive increment for the level adjusting circuit of the A/D
reference. The larger the step the faster the A/D Calibration settles.
CONFIGURATION REGISTER 4 ADDRESS (10h) A/D CAL NEG
Bits 0 - 7
This 8-bit control register contains a binary value used for the negative increment for the level adjusting circuit of the A/D
reference. The number is programmed as 256 - the value wanted since it is a negative number.
CONFIGURATION REGISTER 5 ADDRESS (14h) CCA ANTENNA CONTROL
Bits 7:6
R/W, But Not Used Internally
Bit 5
0 = Normal
1 = A/D timing adjustment during acquisition, deassertion of RXPE required to activate.
HFA3860A
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