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參數(shù)資料
| 型號： | HFA3860A |
| 廠商： | Intersil Corporation |
| 英文描述： | Direct Sequence Spread Spectrum Baseband |
| 中文描述： | 直接序列擴(kuò)頻基帶 |
| 文件頁數(shù)： | 24/39頁 |
| 文件大?。?/td> | 251K |
| 代理商： | HFA3860A |
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Demodulator Performance
This section indicates the typical performance measures for
a radio design. The performance data below should be used
as a guide. In general, the actual performance depends on
the application, interference environment, RF/IF
implementation and radio component selection.
Overall Eb/N0 Versus BER Performance
The PRISM chip set has been designed to be robust and
energy efficient in packet mode communications. The
demodulator uses coherent processing for data
demodulation. The figures below show the performance of
the baseband processor when used in conjunction with the
HSP3724 IF limiter and the PRISM recommended IF filters.
Off the shelf test equipment are used for the RF processing.
The curves should be used as a guide to assess
performance in a complete implementation.
Factors for carrier phase noise, multipath, and other
degradations will need to be considered on an
implementation by implementation basis in order to predict
the overall performance of each individual system.
Figure 16 shows the curves for theoretical DBPSK/DQPSK
demodulation with coherent demodulation and descrambling
as well as the PRISM performance measured for DBPSK
and DQPSK. The theoretical performance for DBPSK and
DQPSK are the same as shown on the diagram. Figure 17
shows the theoretical and actual performance of the MBOK
modes. The losses in both figures include RF and IF radio
losses; they do not reflect the HFA3860A losses alone. The
HFA3860A baseband processing losses from theoretical
are, by themselves, a small percentage of the overall loss.
The PRISM demodulator performs with an implementation
loss of less than 3dB from theoretical in a AWGN
environment with low phase noise local oscillators. For the 1
and 2MBps modes, the observed errors occurred in groups
of 4 and 6 errors. This is because of the error extension
properties of differential decoding and descrambling. For the
5.5MBps and 11MBps modes, the errors occur in symbols of
4 or 8 bits each and are further extended by the
descrambling. Therefore the error patterns are less well
defined.
Clock Offset Tracking Performance
The PRISM baseband processor is designed to accept data
clock offsets of up to
±
25ppm for each end of the link (TX
and RX). This effects both the acquisition and the tracking
performance of the demodulator. The budget for clock offset
error is 0.75dB at
±
50ppm and the performance is shown in
Figure 18. This figure shows that the baseband processor in
the high rate modes is better than at low rates in tracking
clock offsets. The data for this figure and the next one was
taken with the SNR into the receiver set to achieve 1E
-5
BER
with no offset. Then the offset was varied to determine the
change in performance.
Carrier Offset Frequency Performance
The correlators used for acquisition for all modes and for
demodulation in the 1MBps and 2MBps modes are time
invariant matched filter correlators otherwise known as
parallel correlators. They use two samples per chip and are
tapped at every other shift register stage. Their performance
with carrier frequency offsets is determined by the phase roll
rate due to the offset. For an offset of +50ppm (combined for
both TX and RX) will cause the carrier to phase roll 22.5
degrees over the length of the correlator. This causes a loss
of 0.22dB in correlation magnitude which translates directly
to Eb/N0 performance loss. In the PRISM chip design, the
correlator is not included in the carrier phase locked loop
correction, so this loss occurs for both acquisition and data.
In the high rate modes, the data demodulation is done with a
set of correlators that are included in the carrier tracking
loop, so the loss is less. Figure 19 shows the loss versus
carrier offset taken out to +75ppm (120kHz is 50ppm at
2.4GHz).
A Default Register Configuration
The registers in the HFA3860A are addressed with 6-bit
numbers where the lower 2 bits of an 8-bit hexadecimal
address are left as unused. This results in the addresses
being in increments of 4 as shown in table 11.
Table 11 shows the register values for a default 802.11
configuration with dual antennas and various rate
configurations. The data is transmitted as either DBPSK,
DQPSK, BMBOK, or QMBOK depending on the
configuration chosen. It is recommended that you start with
the simplest configuration (DBPSK) for initial test and
verification of the device and/or the radio design. The user
can later modify the CR contents to reflect the system and
the required performance of each specific application.
HFA3860A
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PDF描述 |
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| HFA3860AIV | 3.3V 288-mc CPLD |
| HFA3861AIN96 | Circular Connector; No. of Contacts:21; Series:MS27473; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:22; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:22-21 RoHS Compliant: No |
| HFA3861AIN | 288 MACROCELL 3.3 VOLT ISP CPLD |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HFA3860AEVAL1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| HFA3860AIV | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband |
| HFA3860AIV WAF | 制造商:Harris Corporation 功能描述: |
| HFA3860AIV96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband |
| HFA3860B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:nullDirect Sequence Spread Spectrum Baseband Processor |
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