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參數資料
| 型號： | HFA3842IN96 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Wireless LAN Medium Access Controller |
| 中文描述： | 1 CHANNEL(S), 11M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128 |
| 封裝： | 14 X 20 MM, PLASTIC, MS-026BHB, LQFP-128 |
| 文件頁數： | 17/26頁 |
| 文件大?。?/td> | 512K |
| 代理商： | HFA3842IN96 |
17
Note: All register cycles, including hardware registers,
incur a short wait state on the PC Card bus to ensure the
host cycle is synchronized with the HFA3842's internal
MCLK.
MEMORY MAPPED REGISTERS IN DATA RAM (MM)
1 to 1 correspondence.
Requires memory arbitration, since registers are actually
locations in HFA3842 memory.
Attribute memory access is mapped into RAM as Base-
address + 0x400.
AUX port provides host access to any location in HFA3842
RAM (reserved).
BUFFER ACCESS PATH (BAP)
No 1 to 1 correspondence between register address and
memory address (due to indirect access through buffer
address pointer registers).
Auto increment of pointer registers after each access.
Require memory arbitration since buffers are located in
HFA3842 memory.
Buffer access may incur additional delay for Hardware
Buffer Chaining.
Buffer Access Paths
The HFA3842 has two independent buffer access paths,
which permits concurrent read and write transfers. The
firmware provides dynamic memory allocation between
Transmit and Receive, allowing efficient memory utilization.
On-the-fly allocation of (128-byte) memory blocks as needed
for reception wastes minimal space when receiving
fragments. The HFA3842 hides management of free
memory from the driver, and allows fast response and
minimum data copying for low latency. The firmware
provides direct access to TX and RX buffers based on
Frame ID (FID). This facilitates Power Management queuing,
and allows dynamic fragmentation and defragmentation by
controller. Simple Allocate/Deallocate commands ensure
low host CPU overhead for memory management.
Hardware buffer chaining provides high performance while
reading and writing buffers. Data is transferred between the
host driver and the HFA3842 by writing or reading a single
register location (The Buffer Access Path, or BAP). Each
access increments the address in the buffer memory. Internally,
the firmware allocates blocks of memory as needed to provide
the requested buffer size. These blocks may not be contiguous,
but the firmware builds a linked list of pointers between them.
When the host driver is transferring data through a buffer
access path and reaches the end of a physical memory block,
hardware in the host interface follows the linked list so that the
buffer access path points to the beginning of the next memory
block. This process is completely transparent to the host driver,
which simply writes or reads all buffer data to the same register.
If the host driver attempts to access beyond the end of the
allocated buffer, subsequent writes are ignored, and reads will
be undefined.
PHY Interface
The HFA3842 is intended to support the PRISM family of
Baseband processors with no additional components. This
family currently includes the HFA3860B, HFA3861B, HFA3861
and HFA3863 baseband processors and the other ICs in the
PRISM radio chip set. (Other baseband processors may be
supported with custom firmware. See your sales representative
for more information). The HFA3842 interfaces to the HFA386X
baseband processors through two serial interfaces. The
Modem Management Interface (MMI) is used to read and write
internal registers in the baseband processor and access per-
packet PLCP information. The Modem Data Interface (MDI)
provides the receive and transmit data paths which transfer the
actual MPDU data.
Serial Control Port (MMI)
The HFA3842 has a serial port that is used to program the
baseband processor. There are individual chip selects and
shared clock and data lines.
The MMI is used to program the registers and functionality of
the PHY baseband processor.
TABLE 6. MEMORY MAPPED REGISTER
I/O OFFSET
00
02
04
06
08
0A
0C
0E
10
20
22
24
18
1C
36
1A
1E
38
30
32
34
14
28
2A
2C
3A
3C
3E
NAME
TYPE
MM
MM
MM
MM
MM
MM
MM
MM
MM
MM
MM
MM
MM
MM
BAP
MM
MM
BAP
HW
HW
HW
MM
MM
MM
MM
HW
HW
(Reserved)
Command
Param0
Param1
Param2
Status
Resp0
Resp1
Resp2
InfoFID
RxFID
AllocFID
TxComplFID
BAP Select0
BAP Offset0
BAP Data0
BAP Select1
BAP Offset1
BAP Data1
EvStat
IntEn
EvAck
Control
SwSupport0
SwSupport1
SwSupport2
AuxBase
AuxOffset
AuxData
HFA3842
相關PDF資料 |
PDF描述 |
|---|---|
| HFA3842 | Wireless LAN Medium Access Controller |
| HFA3842IN | Wireless LAN Medium Access Controller |
| HFA3860AIV96 | Circular Connector; No. of Contacts:5; Series:MS27473; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:10; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:10-5 RoHS Compliant: No |
| HFA3860A | Direct Sequence Spread Spectrum Baseband |
| HFA3860AIV | 3.3V 288-mc CPLD |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HFA3860 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:11 Mbps Direct Sequence Spread Spectrum Baseband Processor |
| HFA3860A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband |
| HFA3860AEVAL1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| HFA3860AIV | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband |
| HFA3860AIV WAF | 制造商:Harris Corporation 功能描述: |
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